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* | | armv8/ls2085a: Update SoC README for DDR layoutPrabhakar Kushwaha2015-07-20-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update SoC README to provide details of - Memory regions - Memory used by MC and Debug server Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | armv8/fsl-ch3: Add support to print SoC personalityPrabhakar Kushwaha2015-07-20-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | armv8/fsl-lsch3: Fix DDR speed messageYork Sun2015-07-20-2/+2
| | | | | | | | | | | | | | | | | | | | | DDR speed should be in MT/s, not MHz. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
* | | armv8/ls2085a: call ft_pcie_setup() to change dts statusPrabhakar Kushwaha2015-07-20-0/+4
| |/ |/| | | | | | | | | | | | | | | call ft_pci_setup() to disable PCIe dts node if corresponding PCIe controller is disabled according to RCW Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-07-14-1/+8
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| * stv0991: configure clock & pad muxing for qspiVikas Manocha2015-07-03-1/+8
| | | | | | | | | | | | | | | | stv0991 has cadence qspi controller for flash interfacing, this patch configures the device pads & clock for the controller. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-07-07-4/+3
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| * \ Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-07-07-122/+674
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| * | armv7: better comment in start.SPavel Machek2015-07-07-4/+3
| | | | | | | | | | | | | | | | | | | | | Fix big/small letters in comment. Signed-off-by: Pavel Machek <pavel@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-07-05-6/+11
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| * | | sunxi: Add support for UART0 in PB pin group on A33Chen-Yu Tsai2015-07-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A33 adds a pinmux function for UART0 in the PB pin group. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: rsb: Enable R_PIO clock before configuring external pinsChen-Yu Tsai2015-07-05-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original code was configuring the external pins after enabling the R_PIO clock, which meant the configuration never made it to the pin controller the first time in SPL. Why this was working before is uncertain. Maybe the state was left from a previous boot sequence, or RSB just happened to be the default configuration. However with some A33 chips, SPL failed to configure the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev board. Reordering the calls fixed this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: hardware-feature-specific function index defines for PORT F UART0Chen-Yu Tsai2015-07-05-4/+4
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function index defines") renamed all GPIO index defines, but missed the PORT F UART0 setup functions. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-07-03-1/+8
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: configs/tbs2910_defconfig configs/tqma6q_mba6_mmc_defconfig configs/tqma6q_mba6_spi_defconfig configs/tqma6s_mba6_mmc_defconfig configs/tqma6s_mba6_spi_defconfig include/configs/mx6_common.h Signed-off-by: Tom Rini <trini@konsulko.com>
| * | imx: mx6 correct get_cpu_revPeng Fan2015-06-27-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DIGPROG register map: 23 ------- 16 | 15 ------ 8 | 7 --- 0 | Major upper | Major Lower | Minor | We also need to account for Major Lower. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | arm: mx6: tqma6: CPU type selection via KconfigMarkus Niebel2015-06-27-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the first patch to remove the CONFIG_SYS_EXTRA_OPTIONS. This patch implements CPU type selection from Kconfig. Further Kconfig stuff is added later. Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
* | | Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal ↵Ian Campbell2015-06-28-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND memory" This reverts commit f76eba38b3eda905ff3bdc18dd1240d3dcbc6e5a. This patch did not have a full and proper copyright/S-o-b chain. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Conflicts: include/configs/sun6i.h include/configs/sun8i.h
* | | Move default y configs out of arch/board KconfigJoe Hershberger2015-06-25-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some archs/boards specify their own default by pre-defining the config which causes the Kconfig system to mix up the order of the configs in the defconfigs... This will cause merge pain if allowed to proliferate. Remove the configs that behave this way from the archs. A few configs still remain, but that is because they only exist as defaults and do not have a proper Kconfig entry. Those appear to be: SPIFLASH DISPLAY_BOARDINFO Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates, drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: Change configuration to prevent DDR reset control from EMIFNishanth Menon2015-06-19-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA7/AM57xx devices can be operated in many different configurations. When the SoC is supposed to support a configuration where low power mode state may involve the SoC completely powered off and DDR is in self refresh, SoC EMIF controller should not be the master of the reset signal and an external entity might be in control of things. The default configuration of Linux on TI evms involve not powering off the voltage rails (due to various reasons including reliability concerns) and must not allow DDR reset to be controlled by EMIF. On platforms where external entity might control the reset signal, this configuration will be a "dont care". Fixes: 536d87470869 ("ARM: DRA7: Update DDR IO registers") Tested-by: Keerthy <j-keerthy@ti.com> Acked-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | sun6i: cpu_reset: Do not return from cpu_reset()Hans de Goede2015-06-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently on sun6i after a "reset" the prompt returns and the user can even type stuff until the watchdog triggers and does the actual reset. This is somewhat unexpected behavior for the "reset" command, this commit adds an endless loop to wait for the watchdog to trigger so that we do not return to the prompt. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | ARM: DRA7: emif: Fix DDR init sequence during warm resetLokesh Vutla2015-06-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after warm reset, emif needs to be configured to bring it back to a known state. So configure EMIF during warm reset. Reported-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | am33xx: Re-enable SW levelling for DDR2Tom Rini2015-06-15-34/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recent changes for hw leveling on am33xx were not intended for DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config value to check against. This lets us pass in the value we would use to configure, when we have not yet configured the board yet. In other cases update the call to be as functional as before and check an already programmed value in. Tested-by: Yan Liu <yan-liu@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: BeagleBoard-x15: Enable i2c5 clocksLokesh Vutla2015-06-15-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | On AM57xx evm I2C5 is used to detect the LCD board by reading the EEPROM present on the bus. Enable i2c5 clocks to help that. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: Add support for manual mode configurationLokesh Vutla2015-06-12-1/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "manual mode" also programmed, when predefined delay characteristics cannot be used for the interface. struct iodelay_cfg_entry is introduced for populating manual mode IO timings. For configuring manual mode, along with the normal pad configuration do the following steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux) - Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL. And pass the offset of the CFG_XXX register in iodelay_cfg_entry. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Add support for IO delay configurationLokesh Vutla2015-06-12-0/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA7, in addition to the regular muxing of pins, an additional hardware module called IODelay which is also expected to be configured. This "IODelay" module has it's own register space that is independent of the control module. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay recalibration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do muxing as part of IOdelay recalibration. IODELAY recalibration sequence: - Complete AVS voltage change on VDD_CORE_L - Unlock IODLAY config registers. - Perform IO delay calibration with predefined values. - Isolate all the IOs - Update the delay mechanism for each IO with new calibrated values. - Configure PAD configuration registers - De-isolate all the IOs. - Relock IODELAY config registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Make do_set_mux32() genericLokesh Vutla2015-06-12-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | do_set_mux32() is redefined in dra7xx and beagle_x15 boards. IO delay recalibration sequence also needs this. Making it generic to avoid duplication. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL registerLokesh Vutla2015-06-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | When DLL_CALIB_INTERVAL is set, an extra delay is added which is not required and it consumes EMIF bandwidth. So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7: Update DDR IO registersLokesh Vutla2015-06-12-8/+8
| | | | | | | | | | | | | | | | | | | | | Update DDR IO register values. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: Update DDR IO configurationLokesh Vutla2015-06-12-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | DDRIO_2 and LPDDR2CH1_1 registers are not present for DRA7. So not configuring these registers for DRA7xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA72-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on DRA7-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: DDR3: Add support for HW levelingLokesh Vutla2015-06-12-24/+198
|/ / | | | | | | | | | | | | | | DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | dts: Disable device tree for SPL on all boardsSimon Glass2015-06-10-0/+10
| | | | | | | | | | | | | | We plan to enable device tree in SPL by default. Before doing this, explicitly disable it for all boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Allow cleanup_before_linux() without disabling cachesSimon Glass2015-06-10-18/+29
| | | | | | | | | | | | | | | | This function is used before jumping to U-Boot, but in that case we don't always want to disable caches. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
* | sunxi: Request macpwr gpio before using itHans de Goede2015-06-10-0/+1
| | | | | | | | | | | | | | | | This fixes ethernet no longer working on boards which use a gpio to enable the phy. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-06-08-5/+12
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| * | arm: vf610: Add clock support for DSPIBhuvanchandra DV2015-06-08-0/+7
| | | | | | | | | | | | Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
| * | mxs: Do not disable bo detection when DC-DC is already enabledStefan Wahren2015-06-01-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case the DC-DC is already enabled mxs_enable_4p2_dcdc_input() returns without reenabling brown out detection. So fix this issue by moving the return before brown out deactivation. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | | sunxi: usb_phy: Swap check for disconnect thresholdHans de Goede2015-06-04-3/+3
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit the code for determining the disconnect threshold was checking for sun4i or sun6i assuming that those where the exception and that newer SoCs use a disconnect threshold of 2 like sun7i does. But it turns out that newer SoCs actually use a disconnect threshold of 3 and sun5i and sun7i are the exceptions, so check for those instead. Here are the settings from the various Allwinner SDK sources: sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2); sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun8i-h3: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2); Note this commit makes no functional changes for sun4i - sun7i, and changes the disconnect threshold for sun8i to match what Allwinner uses. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-06-01-0/+22
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| * | arm: rmobile: alt: Update to QoS revision 0.31 and 0.321Nobuhiro Iwamatsu2015-06-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This updates r8a7794 QoS to revision 0.31 for ES1 and revision 0.321 for ES2. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: gose: Update to QoS revision 0.311Nobuhiro Iwamatsu2015-06-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This updates r8a7793 QoS to revision 0.311. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: koelsch: Update to QoS revision 0.411Nobuhiro Iwamatsu2015-06-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This updates r8a7791 QoS to revision 0.411. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: lager: Update to QoS revision 0.973Nobuhiro Iwamatsu2015-06-01-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | This updates r8a7790 QoS to revision 0.973. This commit can changed from KConfig to fit contents of the QoS. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | ARM: sunxi: Share sun6i PSCI backend with sun8iChen-Yu Tsai2015-05-29-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | sun8i can share the PSCI backend with sun6i. Only difference is sun8i does not have CPU power clamp controls. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | ARM: sunxi: Add sun6i specific PSCI implementationChen-Yu Tsai2015-05-29-0/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds PSCI support for sun6i. So far it only supports the PWR_ON method. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | ARM: sunxi: Make PSCI code sun7i specificChen-Yu Tsai2015-05-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PSCI code only works for sun7i. Rename it with _sun7i suffix, and build only if building for sun7i. This paves the way for adding PSCI support for other platforms. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | ARM: sunxi: Document registers in PSCI codeChen-Yu Tsai2015-05-29-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PSCI CPU_ON code accesses quite a few registers. Document their names to make it easier to cross reference. Also explain "lock cpu" and "unlock cpu" as enabling/disabling debug access. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memoryDaniel Kochmański2015-05-29-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support to the sunxi SPL to load u-boot from the internal NAND. Note this only adds support to access the boot partitions to load u-boot, full NAND support to load the kernel, etc. from the nand data partition will come later. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sun9i: Basic sun9i (A80) supportHans de Goede2015-05-29-0/+9
| | | | | | | | | | | | | | | | | | | | | Add initial sun9i (A80) support, only uart + mmc are supported for now. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
generated by cgit v1.1 at 2024-11-15 05:32:06 +0000