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* OMAP5: ADD precalculated timings for ddr3Lokesh Vutla2012-07-07-1/+50
| | | | | | | Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: Configure the io settings for omap5432 uevm boardLokesh Vutla2012-07-07-19/+79
| | | | | | This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: ADD chip detection for OMAP5432 SOCLokesh Vutla2012-07-07-1/+9
| | | | | | This patch adds chip detection for OMAP5432 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* DaVinci: fix ddr2 vtp i/o calibrationTroy Kisky2012-07-07-4/+3
| | | | | | | | | | | | | | | | | | | | | Previously, only the low 5 bits (NCH) were being transfered from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed. VTP_RECAL should be bit 15, not 18. The only mainline board affected by this change is davinci_sonata. The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT. However, if the program that loads u-boot on these boards copied the code from u-boot, they will need fixed as well. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Please get tested by acks before applying, where tested by means an overnight memory test. Thanks Troy
* ARM: OMAP5: Align memory used for testing to the power of 2SRICHARAN R2012-07-07-0/+3
| | | | | | | | | | | | get_ram_size checks the given memory range for valid ram, but expects the size of memory to be aligned to the power of 2. In case of OMAP5 evm board the memory available is 2GB - 16MB(used for TRAP section) = 2032MB. So always ensure that the size of memory used for testing is aligned to the power of 2. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP5: dmm: Create a tiler trap section.SRICHARAN R2012-07-07-3/+3
| | | | | | | | | | | | | | | | | The unmapped entries in tiler space are set with values 0xFF. So creating a DMM section of size 16MB at 0xFF000000 with ADDRSPACE set to 0x2. This way all the unmapped entry accesses to tiler will be trapped by the EMIF and a error response is sent to the L3 interconnect. L3 errors are inturn reported to MPU. Note that here the tiler trap section is overlapping with the actual ddr physical space and we lose 16MB out of the total 2GB. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4+: dmm: Take care of overlapping dmm and trap sections.SRICHARAN R2012-07-07-2/+18
| | | | | | | | | | | | | The DMM sections can be overlapping with each other, with sections 3 to 0 having the highest to lowest priority in that order. There could also be a section that is used trap the unmapped Tiler entries and this trap section could be overlapping with the actual sdram area. So take care of the above scenarios while calculating the size of the actual ram. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* am33xx: Do not call init_timer twiceTom Rini2012-07-07-14/+16
| | | | | | | We do not need to call init_timer both in SPL and U-Boot itself, just SPL needs to initialize the timer. Signed-off-by: Tom Rini <trini@ti.com>
* arm: Tegra: Use ODMDATA from BCT in IRAMTom Warren2012-07-07-1/+21
| | | | | | | | | | | | | | | | Walk the BIT and BCT to find the ODMDATA word in the CustomerData field and put it into Scratch20 reg for use by kernel, etc. Built all Tegra builds OK; Booted on Seaboard and saw ODMDATA in PMC scratch20 was the same as the value in my burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities will have to specify the odmdata (nvflash --odmdata n) on the command line or via a cfg file, or built in to their BCT. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* tegra: override compiler flags for low level init codeamartin@nvidia.com2012-07-07-2/+5
| | | | | | | | | | | | | | | Override -march setting for tegra to -march=armv4t for files that are necessary for low level init on tegra. The recent change to use -march=armv7-a for armv7 caused a regression on tegra because tegra starts boot on a arm7tdmi processor before transferring control to the cortex-a9. While still executing on the arm7tdmi there are calls to getenv_ulong() and memset() that cause an illegal instruction exception if compiled for armv7. Signed-off-by: Allen Martin <amartin@nvidia.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Correct PLL access in ap20.c and clock.cSimon Glass2012-07-07-4/+6
| | | | | | | | | | | | | Correct this warning seen by Albert: ap20.c:44:18: warning: array subscript is above array bounds There is a subtle bug here which currently causes no errors, but might in future if people use PCI or the 32KHz clock. So take the opportunity to correct the logic now. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add SDMMC1 on SDIO1 funcmux entryStephen Warren2012-07-07-0/+7
| | | | | | | This will be used on TrimSlice. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add SDIO1 funcmux entry for UARTALucas Stach2012-07-07-0/+7
| | | | | | | | | | | | | | | This is based on top of: tegra: add alternate UART1 funcmux entry tegra: add UART1 on GPU funcmux entry v2: remove enum change Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <twarren@nvidia.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add UART1 on GPU funcmux entryStephen Warren2012-07-07-1/+8
| | | | | | | TrimSlice uses UART1 on the GPU pingroup. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add alternate UART1 funcmux entryStephen Warren2012-07-07-2/+25
| | | | | | | | (In at least some configurations) Whistler uses UART1 on pingroups UAA, UAB. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* arch/arm/cpu/ixp/npe/npe.c: Fix build warningAnatolij Gustschin2012-05-22-1/+1
| | | | | | | | Fix: npe.c: In function 'npe_initialize': npe.c:630:13: warning: assignment from incompatible pointer type Signed-off-by: Anatolij Gustschin <agust@denx.de>
* arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xxMatt Porter2012-05-15-0/+16
| | | | | | | | | | | | | | | | In warm reset conditions on OMAP36xx/AM/DM37xx the rom code incorrectly sets the DPLL4 clock input divider to /6.5 which is an invalid value unless the input clock is 13MHz. When a JTAG emulator is attached, a warm reset is necessary after the emulator gains control of the process. This results in a loss of serial output due to the invalid DPLL4 settings. This patch fixes the issue by resetting the DPLL4 clock input divider to /1 when the input clock is not 13MHz. AM/DM37x TRM section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only used when the input clock is 13MHz. Signed-off-by: Matt Porter <mporter@ti.com>
* omap4: do not enable auxiliary coresTero Kristo2012-05-15-4/+0
| | | | | | | | | Booting up these cores (dsp / ivahd / cortex-m3) is bad without firmware running on them, and they will hang preventing any kind of sleep transitions later on with the kernel. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: R Sricharan <r.sricharan@ti.com>
* omap4: do not enable fs-usb moduleTero Kristo2012-05-15-2/+0
| | | | | | | If this is done in the bootloader, the FS-USB will later be stuck into intransition state, which will prevent the device from entering idle. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* tegra2: trivially enable 13 mhz crystal frequencyLucas Stach2012-05-15-1/+4
| | | | | | | This is needed for upcoming Toradex Colibri T20 upstream support. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add keyboard support to funcmuxSimon Glass2012-05-15-0/+16
| | | | | | | Add funcmux support for the default keyboard mapping. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Setup PMC scratch info from ap20 setupYen Lin2012-05-15-0/+6
| | | | | | | | Save SDRAM parameters into the warmboot scratch registers Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add warmboot implementationYen Lin2012-05-15-0/+719
| | | | | | | | | Add code to set up the warm boot area in the Tegra CPU ready for a resume after suspend. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add PMU to manage power suppliesJimmy Zhang2012-05-15-0/+71
| | | | | | | | | | | Power supplies must be adjusted in line with clock frequency. This code provides a simple routine to set the voltage to allow operation at maximum frequency. - Split PMU code into separate TPS6586X driver Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add EMC support for optimal memory timingsJimmy Zhang2012-05-15-0/+287
| | | | | | | | Add support for setting up the memory controller parameters. Boards can set up an appropriate table in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add tegra_get_chip_type() to detect SKUSimon Glass2012-05-15-0/+36
| | | | | | | | | | We want to know which type of chip we are running on - the Tegra family has several SKUs. This can be determined by reading a fuse register, so add this function to ap20. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add crypto library for warmboot codeYen Lin2012-05-15-0/+266
| | | | | | | | Provides an interface to aes.c for the warmboot code. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add functions to access low-level Osc/PLL detailsSimon Glass2012-05-15-0/+32
| | | | | | | | Add clock_ll_read_pll() to read PLL parameters and clock_get_osc_bypass() to find out if the Oscillator is bypassed. These are needed by warmboot. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Move ap20.h header into arch locationSimon Glass2012-05-15-105/+3
| | | | | | | | We want to include this from board code, so move the header into an easily-accessible location. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Add abs() macro to return absolute valueSimon Glass2012-05-15-2/+0
| | | | | | | | | This macro is generally useful to make it available in common. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* i.MX28: Avoid redefining serial_put[cs]()Marek Vasut2012-05-15-0/+2
| | | | | | | | | | | | Do not define serial_putc() and serial_puts() calls if CONFIG_SPL_SERIAL_SUPPORT is set. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX28: Add battery boot components to SPLMarek Vasut2012-05-15-8/+92
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Reorder battery status functions in SPLMarek Vasut2012-05-15-64/+56
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Add LRADC init to i.MX28 SPLMarek Vasut2012-05-15-1/+100
| | | | | | | | | | This code is part of battery boot support for i.MX28. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Shut down the LCD controller before resetMarek Vasut2012-05-15-1/+8
| | | | | | | | | | | | If the LCD controller is on before the CPU goes into reset, the traffic on LCDIF data pins interferes with the BootROM's boot mode sampling. So shut the controller down. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Implement boot pads sampling and reportingMarek Vasut2012-05-15-0/+52
| | | | | | | | | | | This patch implements code that samples i.MX28 boot pads and reports boot mode accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Improve passing of data from SPL to U-BootMarek Vasut2012-05-15-18/+16
| | | | | | | | | | | | Pass memory size from SPL via structure located in SRAM instead of SCRATCH registers. This allows passing more data about boot from SPL to U-Boot, like the boot mode pads configuration. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* i.MX28: Add delay after CPU bypass is clearedMarek Vasut2012-05-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This solves issues when larger amount of DRAM is used, like 256MB. Behave the same in case of CPU bypass as we do in case of EMI bypass, but wait 15 ms. We need to wait until the clock domain stabilizes. This issue seemed to have been caused by not waiting after frobbing with the CPU bypass, it was unrelated to memory, but had a direct impact, causing trouble. This was yet another X-File of the imx-bootlets, sigh. The conclusion is, trying a semi-random delay (there is delay after the EMI bypass change), the issue is fixed. Another possible explanation is that we do not do the "simple memory test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of the memory, while also outputing something on the serial port). This might have caused the similar delay in the imx-bootlets and therefore they didn't need to add this explicitly. For now, this seems good fix enough, but to me, whole that memory init code in imx-bootlets is completely flunked and it'd need deeper investigation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
* imx: Add u-boot.imx as target for ARM9 i.MX SOCsTimo Ketola2012-05-15-0/+6
| | | | | Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX25: esdhc: Add mxc_get_clock infrastructureTimo Ketola2012-05-15-0/+27
| | | | | | | | | Defining CONFIG_FSL_ESDHC brings in a call to get_clocks, so let's implement get_clocks function. This is how it seems to be implemented elsewhere. Signed-off-by: Timo Ketola <timo@exertus.fi> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX6: add enable_sata_clock()Eric Nelson2012-05-15-0/+31
| | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
* i.MX6: Add ANATOP regulator initDirk Behme2012-05-15-0/+30
| | | | | | | | | | | | | | | | Init the core regulator voltage to 1.2V. This is required for the correct functioning of the GPU and when the ARM LDO is set to 1.225V. This is a workaround to fix some memory clock jitter. Note: This should be but can't be done in the DCD. The bootloader prevents access to the ANATOP registers. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Jason Chen <b02280@freescale.com> CC: Jason Liu <r64343@freescale.com> CC: Ranjani Vaidyanathan <ra5478@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <festevam@gmail.com>
* Revert "i.MX28: Enable additional DRAM address bits"Marek Vasut2012-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 69d26d09de1cb93e0a09ca71d9f0d41a66f0756a. Apparently, this commit got mainline only because of out-of-tree port and causes breakage on board that is mainline. Revert. Reason: * The OOT board has 512MB of DRAM, enabling this additional address line enabled it to work fine with 512MB of RAM. * Every mainline port has max. 256MB of DRAM, therefore this revert has no impact on any mainline port * Though this caused a problem with new M28 board with 256MB of DRAM where the chips are wired differently. The patch-to-be-reverted caused the DRAM to behave like this: [128MB chunk #1][128MB chunk #1 again][128MB chunk #2][128MB chunk #2 again] Therefore to retain the current one-memory-init-rules-them-all situation, revert this patch until another board emerges and will actually be pushed mainline that needs different setup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
* mx53loco: Allow to print CPU information at a later stageFabio Estevam2012-05-15-1/+1
| | | | | | | | | | | Print CPU information within board_late_init(). This is in preparation for adding 1GHz support, which requires programming a PMIC via I2C. As I2C is only available after relocation, print the CPU information later at board_late_init(), so that the CPU frequency can be printed correctly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: Add clock config interfaceFabio Estevam2012-05-15-4/+444
| | | | | | | | | | | mx5: Add clock config interface Add clock config interface support, so that we can configure CPU or DDR clock in the later init Signed-off-by: Jason Liu <jason.hui@linaro.org> Signed-off-by: Eric Miao <eric.miao@linaro.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx-common: Factor out get_ahb_clk()Fabio Estevam2012-05-15-32/+19
| | | | | | | | | get_ahb_clk() is a common function between mx5 and mx6. Place it into imx-common directory. Cc: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX53: add function to set SATA clock to internalStefano Babic2012-05-15-0/+24
| | | | | | | | | | | | | | | | | | | | | The MX53 SATA interface can use an internal clock (USB PHY1) instead of an external clock. This is an undocumented feature, but used on most Freescale's evaluation boards, such as MX53-loco. As stated by Freescale's support: Fuses (but not pins) may be used to configure SATA clocks. Particularly the i.MX53 Fuse_Map contains the next information about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C) '00' - 100MHz (External) '01' - 50MHz (External) '10' - 120MHz, internal (USB PHY) '11' - Reserved Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
* MX5: Add definitions for SATA controllerStefano Babic2012-05-15-0/+2
| | | | | | | | | Add base address and MXC_SATA_CLK to return the clock used for the SATA controller. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Dirk Behme <dirk.behme@de.bosch.com>
* EXYNOS: add LCD and MIPI DSI clock interface.Donghwa Lee2012-05-15-0/+184
| | | | | | | | | To sets up lcd and mipi clock in EXYNOS display driver, added clock interface. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS: definitions of system resgister and power management registers.Donghwa Lee2012-05-15-1/+103
| | | | | | | | | This is definitions of system registers and power mananagement registers for EXYNOS SoC. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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