Commit message (Expand) | Author | Age | Lines | |
---|---|---|---|---|
* | armv8/mmu: Set bits marked RES1 in TCR | Thierry Reding | 2015-10-15 | -3/+3 |
* | armv8: fsl-lsch3: Rewrite MMU translation table entries | Alison Wang | 2015-09-01 | -4/+13 |
* | ARM: cache: implement a default weak flush_cache() function | Wu, Josh | 2015-08-12 | -8/+0 |
* | ARM: cache: add an empty stub function for invalidate/flush dcache | Wu, Josh | 2015-08-12 | -8/+0 |
* | armv8: caches: Added routine to set non cacheable region | Siva Durga Prasad Paladugu | 2015-07-31 | -0/+36 |
* | armv8/cache: Fix page table creation | Thierry Reding | 2015-07-28 | -2/+2 |
* | armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack | York Sun | 2015-02-24 | -7/+11 |
* | ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC | York Sun | 2014-07-03 | -1/+6 |
* | ARMv8: Adjust MMU setup | York Sun | 2014-07-03 | -30/+20 |
* | armv8/cache: Change cache invalidate and flush function | York Sun | 2014-04-07 | -1/+2 |
* | armv8/cache: Consolidate setting for MAIR and TCR | York Sun | 2014-04-07 | -3/+19 |
* | arm64: core support | David Feng | 2014-01-09 | -0/+219 |