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* | | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-19-14/+173
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| * \ \ Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-02-11-246/+29
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| * | | | ARM: imx6: fix wrong fec clkMarkus Niebel2014-02-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | imx_get_fecclk() returns enet_ref instead of ipg. Since the clock is used to calculate the prescaler for the MDIO interface wrong values can be calculated. Tested on a custom MX6S board with 100MBit interface Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
| * | | | mx6: Enable L2 cache supportFabio Estevam2014-02-11-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add L2 cache support and enable it by default. Configure the L2 cache in the same way as done by FSL kernel: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | | mx6: Distinguish mx6dual from mx6quadFabio Estevam2014-02-11-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when we boot a mx6dual U-boot reports that it is a mx6quad. Report it as MX6D instead: CPU: Freescale i.MX6D rev1.2 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| * | | | imx6: make sure MMDC_CHx_MASK is clear to avoid warm reset failureAnson Huang2014-02-11-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot ROM may mask MMDC_CHx_MASK in CCM_CCDR(such as i.MX6SL TO1.2), it will cause warm reset fail, need to clear this MMDC_CHx_MASK field to make sure all the i.MX6 series SOCs reset function work. Otherwise, uboot "reset" command will fail, tested on i.MX6SL EVK board with TO1.2. Signed-off-by: Anson Huang <b20788@freescale.com>
| * | | | imx6: ensure AHB clock is 132MHz in low freq boot modeAnson Huang2014-02-11-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For low freq boot mode(ARM boot up with 396MHz), ROM will not set AHB clock to 132MHz, and the reset value of AHB divider is incorrect which will lead to wrong AHB rate, need to correct it. To enable low freq boot mode, need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL SabreSD board and i.MX6SL EVK board. Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com>
| * | | | ARM: mx6: Add PCI express clock configurationMarek Vasut2014-01-26-10/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the SATA clock enabling function and add PCI express clock enabling function. The SATA clock enabling function starts up the 100MHz SATA reference PLL in ENET_PLL register, but the code can be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull this code into separate function. Moreover, add the PCIe clock enabling code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | ARM: armv7: Make indirect vector addresses globlMarek Vasut2014-01-26-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make indirect vectors addresses global, so they can be replaced by various code that needs to do so. For example the MX6 PCI express driver needs to temporarily replace data abort handler when reading the config space. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | | Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-01-26-3/+15
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* | | | | | arm: zynq: correct the argument to lldivSiva Durga Prasad Paladugu2014-02-19-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Typecast the argument with unsigned long long for proper calculation of lldiv Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | | zynq: Add support for U-BOOT SPLMichal Simek2014-02-19-2/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPL is using ps7_init.c/h files which are generated from design tools which have to be copied to boards/xilinx/zynq folder before compilation. BSS section is moved to SDRAM because fat support requires more space than SRAM size. Added: - MMC and QSPI support - Boot OS directly from SPL - Enable SPL command Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | | | | zynq: Update CLK in bdinfoMichal Simek2014-02-19-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM has specific clk entries which should be also setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | | zynq: Implement dump clock commandSoren Brinkmann2014-02-19-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable and implement dump clock command which shows soc frequencies. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | | net: zynq_gem: Calculate clock dividers dynamicallySoren Brinkmann2014-02-19-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove hard coded clock divider setting and use the Zynq clock framework to dynamically calculate appropriate dividers at run time. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | | net: zynq_gem: Move RCLK details out of driverSoren Brinkmann2014-02-19-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GEM driver should not need to know about Zynq specific details of RCLK related registers and bitfields in the SLCR. Move those details to the slcr driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | | zynq: timer: Fix hangs if network activity attempted after about one hourMichal Simek2014-02-19-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex-A9 MPCore TRM' from ARM (ARM DDI 0407G ID072711) describes in the section 4.1.1 how this value calculation should be done. This patch fixes the problem if network activity such as ping or tftp is attempted after u-boot has been idle for an hour, it hangs, and cannot control-C out of it. Signed-off-by: Uday Hegde <udayh@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | | zynq: timer: Migrate to zynq clock frameworkSoren Brinkmann2014-02-19-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove hardcoded frequencies in favor of Zynq clock framework. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | | zynq: Provide a framework to read clock frequenciesSoren Brinkmann2014-02-19-0/+641
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | | zynq: Enable dcache supportMichal Simek2014-02-19-0/+8
| |_|_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | Enable dcache. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-02-17-307/+166
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| * | | | | zynq: Fix elf header generationMichal Simek2014-02-13-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is here because of: "arm: keep all sections in ELF file" (sha1: 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7) Our tools expect to have elf with only LOAD header. Without this fix also PHDR, INTERP and DYNAMIC headers are available in ELF. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-13-69/+22
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| | * | | | | exynos: clock: use the clear and set bits macros.Inha Song2014-02-10-65/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use setbits/clrbits macro instead of readl/writel function. (Suggested by Wolfgang) Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | | | | exynos: clock: fixed that cfg is set to wrong value.Inha Song2014-02-10-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixed that cfg value is set to wrong value. Because it didn't read the related register. Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | | | | exynos: pinmux: remove unnecessary routineMinkyu Kang2014-02-05-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because of the list of peripherals is not sequential, such a routine does not check for valid correctly. Error check will be done when call the exynos_pinmux_config function. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
| | * | | | | exynos: pinmux: remove unnecessary defineMinkyu Kang2014-02-05-1/+1
| | | |_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | The value of PERIPH_ID_COUNT was wrong, and unnecessary. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | | | ARM: tegra: Add CPU (armv7) files for Tegra124Tom Warren2014-02-03-0/+16
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These files are for code that runs on the CPU (A15) on Tegra124 boards. At this time, there is no A15-specific code here. The warmboot/LP0 files aren't included as that code hasn't been ported yet. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-29-238/+29
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| | * | | DRA7: add ABB setup for MPU voltage domainNishanth Menon2014-01-24-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch adds modification to shared omap5 abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain at OPP_NOM. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| | * | | DRA7: Add support for ES1.1 silicon ID codeNishanth Menon2014-01-24-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support for ES1.1 IDCODE change. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| | * | | ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALLJassi Brar2014-01-24-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| | * | | ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALLJassi Brar2014-01-24-226/+0
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* | | | SPL: Add CONFIG_SUPPORT_EMMC_BOOT support to CONFIG_SPL_FRAMEWORKTom Rini2014-02-07-1/+12
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use the switch CONFIG_SUPPORT_EMMC_BOOT today to enable some additional features of the eMMC boot partitions. Add support for being told that we have booted from one of these partitions to the spl framework and implement this on TI OMAP/related. Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | | ARM: merge commonly-defined PLATFORM_RELFLAGSMasahiro Yamada2014-01-24-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, all arch/arm/cpu/${CPU}/config.mk except ARMv8 had the same option: $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) This commit moves it into arch/arm/config.mk. If the compiler does not support the option, it is ignored by $(call cc-option,...). So this commit gives no harm to ARMv8. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-01-20-41/+0
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| * mx6: Revert "mx6: soc: Disable VDDPU regulator"Fabio Estevam2014-01-17-41/+0
| | | | | | | | | | | | | | | | | | Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Reported-by: Pierre Aubert <p.aubert@staubli.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-15-1/+7
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| * mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()Fabio Estevam2014-01-15-1/+7
| | | | | | | | | | | | | | | | | | | | Provide an argument to enable_fec_anatop_clock() to specify the clock frequency that will be generated. No changes are made to mx6slevk, which uses the default 50MHz fec clock. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | arm: use canonical sub mnemonicAndreas Bießmann2014-01-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Building some arm boards with older binutils may produce errors like this: ---8<--- crt0.S: Assembler messages: crt0.S:70: Error: register expected, not '#(184)' -- `sub sp,#(184)' --->8--- Use canonical version of the subtract mnemonic to avoid those issues. Reported-by: Alexey Smishlayev <alexey@xtech2.lv> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-14-1/+2
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| * imx6: make use of lldiv(..)Christian Gmeiner2014-01-13-1/+2
| | | | | | | | | | | | | | | | | | | | Commit 762a88ccf8540948fbf8c31b40a29d1e0684a25b introduces a 64-bit division without using the lldiv() function, which pulls in previously unused libgcc stuff. Signed-off-by: Måns Rullgård <mans@mansr.com> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | arm: put .hash, .got.plt and .machine_param back in binariesAlbert ARIBAUD2014-01-14-0/+7
| | | | | | | | | | | | | | | | | | | | | | Some targets will build fine but not boot if sections .hash and .got.plt are not present in the binary. Add them back. Also, Exynos machines require .machine_param section in SPL. Add it. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Tested-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-10-329/+2250
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be added to include/configs/exynos5-dt.h now. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * | zynq: Add support to find bootmodeJagannadha Sutradharudu Teki2014-01-10-0/+6
| |/ | | | | | | | | | | | | | | | | | | | | Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-260/+1911
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| | * Exynos5420: Add support for 5420 in pinmux and gpioRajeshwari Birje2013-12-30-2/+258
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: Add DDR3 initialization for 5420Rajeshwari Birje2013-12-30-56/+469
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: Add clock initialization for 5420Rajeshwari Birje2013-12-30-202/+1184
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-19/+126
| |\ \ | | |/ | |/| | | | | | | | | | | | | | | | Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
generated by cgit v1.1 at 2024-10-08 02:27:33 +0000