Commit message (Expand) | Author | Age | Lines | |
---|---|---|---|---|
* | net: zynq_gem: Calculate clock dividers dynamically | Soren Brinkmann | 2014-02-19 | -5/+8 |
* | net: zynq_gem: Move RCLK details out of driver | Soren Brinkmann | 2014-02-19 | -3/+3 |
* | zynq: Add support to find bootmode | Jagannadha Sutradharudu Teki | 2014-01-10 | -0/+6 |
* | zynq: slcr: Wait 100ms till clk is properly setup | Michal Simek | 2013-08-12 | -1/+1 |
* | Add GPL-2.0+ SPDX-License-Identifier to source files | Wolfgang Denk | 2013-07-24 | -17/+1 |
* | fpga: zynq: Add support for loading bitstream | Michal Simek | 2013-05-06 | -0/+35 |
* | net: gem: Fix gem driver on 1Gbps LAN | Michal Simek | 2013-04-30 | -0/+26 |
* | arm: zynq: Add SLCR support with system reset | Michal Simek | 2013-02-07 | -0/+63 |