Commit message (Expand) | Author | Age | Lines | |
---|---|---|---|---|
* | ARM: non-sec: flush code cacheline aligned | Stefan Agner | 2016-08-12 | -1/+3 |
* | tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0 | Ian Campbell | 2015-05-13 | -0/+5 |
* | ARM: Add board-specific initialization hook for PSCI | Jan Kiszka | 2015-05-13 | -0/+6 |
* | ARM: HYP/non-sec: relocation before enable secondary cores | Peng Fan | 2015-03-01 | -1/+8 |
* | ARM: HYP/non-sec: Make variable gic_dist_addr as a local one | tang yuantian | 2015-01-23 | -2/+7 |
* | ARM: HYP/non-sec: remove MIDR check to validate CBAR | Marc Zyngier | 2014-07-28 | -17/+0 |
* | ARM: HYP/non-sec: allow relocation to secure RAM | Marc Zyngier | 2014-07-28 | -40/+19 |
* | ARM: virtualization: replace verbose license with SPDX identifier | Andre Przywara | 2013-10-07 | -18/+2 |
* | ARM: extend non-secure switch to also go into HYP mode | Andre Przywara | 2013-10-03 | -0/+37 |
* | ARM: add SMP support for non-secure switch | Andre Przywara | 2013-10-03 | -1/+15 |
* | ARM: add C function to switch to non-secure state | Andre Przywara | 2013-10-03 | -0/+122 |