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* sunxi: Move cpu independent code to mach directoryAlexander Graf2016-04-01-4960/+1
| | | | | | | | | | | | Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while most of it is just generic code that could as well be used on an AArch64 SoC. Move all files that are not really tied to armv7 into a new mach-sunxi directory. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: usb_phy: Add support for A83T USB PHYsChen-Yu Tsai2016-03-31-2/+46
| | | | | | | | | The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host, 1 for USB HSIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Print soc-id from sram controller for sun8i boardsHans de Goede2016-03-31-5/+19
| | | | | | | | | As the need for various magic sram pokes has shown this maybe useful info to have. e.g. this shows one of my a23 tablets having an id of 1661 rather then the usual 1650 for the a23. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add conditional magic sram poke for A33Hans de Goede2016-03-31-4/+16
| | | | | | | | | I noticed that for certain SoC versions boot0 does a magic poke when build for A33. I'm not aware of this actually being necessary anywhere, but better safe then sorry. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: A83T: fix 32bit overflow warningvishnupatekar2016-03-23-1/+1
| | | | | | | | | | In mctl_channel_init, (0x50<<26) which overflows 32bit. It was supposed to be 0x50<<16,corrected now. Reported-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Fix gmac not working due to cpu_eth_init no longer being calledHans de Goede2016-03-23-27/+1
| | | | | | | | | | | | | | | | | | | | cpu_eth_init is no longer called for dm enabled eth drivers, this was causing the sunxi gmac eth controller to no longer work in u-boot. This commit fixes this by calling the clock, reset and pinmux setup function from s_init() and enabling the phy power pin (if any) from board_init(). The enabling of phy power cannot be done from s_init because it uses dm and dm is not ready yet at this point. Note that the mdelay is dropped as the phy gets enabled much earlier now, so it is no longer needed. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Tested-by: Karsten Merker <merker@debian.org> Tested-by: Michael Haas <haas@computerlinguist.org>
* sunxi: Add support for USB vbus pin for USB3Hans de Goede2016-03-23-0/+1
| | | | | | | The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Fix clock_twi_onoff for sun9iHans de Goede2016-03-23-2/+2
| | | | | | | | Fix a copy and paste error which caused us to use the uart rather then the twi reset bits in clock_twi_onoff for sun9i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Fix clock_twi_onoff for sun8i-a83Hans de Goede2016-03-23-31/+35
| | | | | | | | | clock_sun8i_a83.c did not contain a clock_twi_onoff implementation at all, this is fixed by moving the clock_sun6i.c implementation, which is correct for the a83 too, to a shared location. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Fix clock_twi_onoff for sun6iHans de Goede2016-03-23-3/+8
| | | | | | | | The clock_sun6i.c implementation was not deasserting the reset for the regular i2c controllers, this commit fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: A23: Fix some revisions needing a different magic sram pokeHans de Goede2016-03-23-3/+19
| | | | | | | | | | | | | I've had this one a23 tablet which would not boot and I've finally figured out what the problem is by looking at the released boot0 code, it seems the magic sram controller poke which we need to do in s_init() depends on the revision of the a23. Specifically this change is needed to get the A23 SoC I have with the following serial to boot: "E6071AB 26Y7". Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: H3: Add support for the host usb-physJelle van der Waa2016-02-23-7/+28
| | | | | | | | Add support for phy 1-3. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> [hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add support for LPDDR3 for A83TVishnu Patekar2016-01-26-5/+49
| | | | | | | | | Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T. Mostly the timing parameters are different from DDR3. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Groundwork to support new dram type for A83TVishnu Patekar2016-01-26-1/+10
| | | | | | | | | | | | | | Different A83T boards have different DRAM types. Banapi M3 has LPDDR3, Allwinner Homlet v1.2 has DDR3. This adds groundwork to support for new DRAM type for A83T. Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must be set in respective board defconfig. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Redundant code cleanup from a83t dram initVishnu Patekar2016-01-26-5/+0
| | | | | | | | This removes the redundant lines of code from mctl_sys_init. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Support PSCI ops on Allwinner H3Chen-Yu Tsai2016-01-26-2/+2
| | | | | | | | | H3 has the same power sequencing procedure as the A31/A31s, which includes the power clamps. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Support H3 CCU security switchesChen-Yu Tsai2016-01-26-0/+18
| | | | | | | | | | | | | | | | H3's CCU includes some switches which disable non-secure access to some of the more critical clock controls, such as MBUS, PLLs, and main platform busses. Configure them to enable non-secure access. For now the only SoC that has this feature is the H3. For other platforms just use a default (weak) empty function so things do not break. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3Chen-Yu Tsai2016-01-26-3/+13
| | | | | | | | | | | | | | | Secure Memory Touch Arbiter is the same thing as the TrustZone Protection Controller found on A31/A31s. Access to many peripherals on the H3 can be controlled by the SMTA, and the settings default to secure access only. This patch supports the new settings, and sets them to allow non-secure access. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add support for the I2C controller which is part of the PRCMJelle van der Waa2016-01-21-0/+22
| | | | | | | | | | | Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> [hdegoede@redhat.com: Minor cleanups] Signed-off-by: Hans de Goede <hdegoede@redhat.com> applied with fixing 2 checkpatch warnings: WARNING: please, no space before tabs Signed-off-by: Heiko Schocher <hs@denx.de>
* sunxi: Fix H3 DRAM DQ read delay configurationJens Kuske2015-12-10-6/+6
| | | | | | | | | | | The read delays were set incorrectly, leading to reliability issues at higher DRAM clock speeds. This commit adjusts this to match the vendor boot0 behaviour. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sun4i: clock: Cleanup some whitespace errorsOlliver Schinagl2015-12-10-3/+3
| | | | | | | | Add some spaces around operators. Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: twi: Enable clocks on sun7iOlliver Schinagl2015-12-10-6/+0
| | | | | | | | | | | | | | | | | Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC but forgot to extend the range check in clock_twi_onoff, resulting in the clock not getting enabled. The range-check is not needed at all, since clock_twi_onoff only gets called with such high indexes when CONFIG_I2C3_ENABLE / CONFIG_I2C4_ENABLE is set and Kconfig already only allows these on sun6i / sun7i. This commit removes the range-check all together fixing i2c bus 4 and 5 not working on sun7i. Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com> [hdegoede@redhat.com] Remove range check instead of extending it Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add support for Allwinner A83T DRAMvishnupatekar2015-12-10-0/+425
| | | | | | | | | | | Add support for A83T dram. Register are different from sun8i A33. init code is similar to A33 dram init. hope we'll shift duplicate code in dram_sun8i_* to dram helper in future. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: clk: add basic clocks for A83Tvishnupatekar2015-12-10-0/+140
| | | | | | | | | | | Add basic clocks pll1, pll5, and some default values from allwinner u-boot. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> [hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz, fixing the mmc support not working [hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to stabilize, fixing cold-booting directly from sdcard not working Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: power: enabled support for axp818vishnupatekar2015-12-10-3/+5
| | | | | | | | | Enabled support for AXP818 in SPL and u-boot. DCDC1, DCDC2, DCDC3 and DCSC5 are enabled. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add support for UART0 in PB pin group on A83Tvishnupatekar2015-12-10-0/+4
| | | | | | | | | | On A83T, PB9,PB10 are UART0 pins. On allwinner A83T Dev board(h8homlet), this uart0 serial connector is exposed. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add Machine Support for A83T SOCvishnupatekar2015-12-10-0/+2
| | | | | | | | | | | Allwinner A83T is octa-core cortex-a7 SOC. This enables support for A83T. SMP is not yet supported. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3Siarhei Siamashka2015-11-22-2/+4
| | | | | | | | | | | | | | | | | | | | | The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz on Allwinner H3 and using PLL6 as the clock source (PLL6/3). This can be verified by reading the value of the AHB1_APB1_CFG_REG register via /dev/mem. It always reads as 0x3180 regardless of the current cpufreq operating point. So this configuration should be safe for use in U-Boot too. PLL6 also needs to be configured before it is used as the clock source, according to the "CCU / Programming Guidelines" section of the Allwinner manual. The current low AHB1 clock speed is limiting the USB transfer speed when booting via FEL. This patch can increase the FEL USB transfer speed from ~510 KB/s to ~950 KB/s. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add H3 DRAM initialization supportJens Kuske2015-11-22-0/+470
| | | | | | | | Based on existing A23/A33 code and the original H3 boot0. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add basic H3 supportJens Kuske2015-11-22-0/+6
| | | | | | | | Add initial sun8i H3 support, only uart + mmc are supported for now. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* spl: mmc: add support for BOOT_DEVICE_MMC2Nikita Kiryanov2015-11-18-9/+1
| | | | | | | | | | | Currently the mmc device that SPL looks at is always mmc0, regardless of the BOOT_DEVICE_MMCx value. This forces some boards to implement hacks in order to boot from other mmc devices. Make SPL take into account the correct mmc device. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com>
* spl: change return values of spl_*_load_image()Nikita Kiryanov2015-11-18-1/+3
| | | | | | | | | | | | | | | | | | | | | | | Make spl_*_load_image() functions return a value instead of hanging if a problem is encountered. This enables main spl code to make the decision whether to hang or not, thus preparing it to support alternative boot devices. Some boot devices (namely nand and spi) do not hang on error. Instead, they return normally and SPL proceeds to boot the contents of the load address. This is considered a bug and is rectified by hanging on error for these devices as well. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans De Goede <hdegoede@redhat.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sunxi: board: Only try to use the MMC related functions if enabledMaxime Ripard2015-10-20-1/+5
| | | | | | | | | | | So far, even if CONFIG_MMC was not enabled the board code was trying to use the MMC-related functions, resulting in linker errors. Protect those calls by an ifdef. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: power: Unify axp pmic function namesHans de Goede2015-10-20-11/+2
| | | | | | | | | Stop prefixing the axp functions for setting voltages, etc. with the model number, there ever is only one pmic driver built into u-boot, this allows simplifying the callers. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Switch to using malloc_simple for the splHans de Goede2015-10-20-0/+1
| | | | | | | | | | common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes, and .data from 0x54c to 0x144 bytes. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@konsulko.com>
* sunxi: retrieve FEL-provided values to environment variablesBernhard Nortmann2015-09-29-1/+2
| | | | | | | | | | | | | | | | | | | This patch extends the misc_init_r() function on sunxi boards to test for the presence of a suitable "sunxi" SPL header. If found, and the loader ("fel" utility) provided a non-zero value for the boot.scr address, then the corresponding environment variable fel_scriptaddr gets set. misc_init_r() also sets (or clears) the "fel_booted" variable depending on the active boot device, using the same logic as spl_boot_device(). The goal is to provide sufficient information (within the U-Boot environment) to make intelligent decisions on how to continue the boot process, allowing specific customizations for the "FEL boot" case. Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Simplify spl board_init_f functionHans de Goede2015-09-29-5/+0
| | | | | | | | crt0.S will both memset the bss sectioan and call board_init_r for us, so there is no need to do either ourselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Enable non-secure access to RTC on sun6i (A31s)Chen-Yu Tsai2015-08-31-0/+24
| | | | | | | | | | | | | | On the A31s the RTC is by default secured. Thus when u-boot loads the kernel in non-secure world, the RTC is unavailable. The SoC has a TrustZone Protection Controller, which can be used to enable non-secure access to the RTC. On the A31 the TZPC doesn't seem to do anything, i.e. changes to its register contents do not affect access to the RTC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sun6i: clock: Add support for the mipi pllHans de Goede2015-08-14-0/+55
| | | | | | | | Add support for the mipi pll, this is necessary for getting higher dotclocks with lcd panels. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: clock: Add clock_get_pll3() helper functionHans de Goede2015-08-14-0/+21
| | | | | | | Add a helper function to get the pll3 clock rate. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: usb-phy: Never power off the usb portsHans de Goede2015-08-08-0/+7
| | | | | | | | | | | | | | | | | | | | | USB devices are not really designed to get the power bounced off and on at them. Esp. USB powered harddisks do not like this. Currently we power off the USB ports both on a "usb reset" and when booting the kernel, causing the usb-power to bounce off and then back on again. This patch removes the powering off calls, fixing the undesirable power bouncing. Note this requires some special handling for the OTG port: 1) We must skip the external vbus check if we've already enabled our own vbus to avoid false positives 2) If on an usb reset we no longer detect that the id-pin is grounded, turn off vbus as that means an external vbus may be present now Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* Kill unneeded #include <linux/kconfig.h>Masahiro Yamada2015-07-27-2/+0
| | | | | | | | | | | | | | | | Because the top-level Makefile forces all the source files to include include/linux/kconfig.h (see the UBOOTINCLUDE define), these includes are redundant. By the way, there are exceptions for the statement above; host programs. In fact, host tools in U-Boot depend on a particular board configuration, although I think they should not. So, some files still include <linux/config.h> to work around build errors on host tools. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Simon Glass <sjg@chromium.org>
* sunxi: musb: Stop treating not having a vbus-det gpio as an errorHans de Goede2015-07-25-3/+1
| | | | | | | | | | | | | On some boards the otg is wired up in host-only mode in this case we have no vbus-det gpio. Stop logging an error from sunxi_usb_phy_vbus_detect() in this case, and stop treating sunxi_usb_phy_vbus_detect() returning a negative errno, as if a charger is plugged into the otg port. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: usb-phy: Add support for reading otg id pin valueHans de Goede2015-07-25-0/+34
| | | | | | | | Add support for reading the id pin value of the otg connector to the usb phy code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: spl: Detect at runtime where SPL was read fromDaniel Kochmański2015-07-24-12/+40
| | | | | | | | | | | | | Make possible using a single `u-boot-sunxi-with-spl.bin` binary for both NAND memory and SD card. Detection where SPL was read from is implemented in `spl_boot_device`. Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu> CC: Roy Spliet <r.spliet@ultimaker.com> Cc: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Some small coding style fixes] Acked-by: Hans De Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.SWang Dongsheng2015-07-20-40/+4
| | | | | | | | | | timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: York Sun <yorksun@freescale.com>
* sunxi: Add support for UART0 in PB pin group on A33Chen-Yu Tsai2015-07-05-0/+4
| | | | | | | | The A33 adds a pinmux function for UART0 in the PB pin group. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: rsb: Enable R_PIO clock before configuring external pinsChen-Yu Tsai2015-07-05-2/+3
| | | | | | | | | | | | | | | | | | | | The original code was configuring the external pins after enabling the R_PIO clock, which meant the configuration never made it to the pin controller the first time in SPL. Why this was working before is uncertain. Maybe the state was left from a previous boot sequence, or RSB just happened to be the default configuration. However with some A33 chips, SPL failed to configure the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev board. Reordering the calls fixed this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: hardware-feature-specific function index defines for PORT F UART0Chen-Yu Tsai2015-07-05-4/+4
| | | | | | | | | | Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function index defines") renamed all GPIO index defines, but missed the PORT F UART0 setup functions. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal ↵Ian Campbell2015-06-28-12/+2
| | | | | | | | | | | | | | NAND memory" This reverts commit f76eba38b3eda905ff3bdc18dd1240d3dcbc6e5a. This patch did not have a full and proper copyright/S-o-b chain. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Conflicts: include/configs/sun6i.h include/configs/sun8i.h
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