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| author | Hans de Goede <hdegoede@redhat.com> | 2015-08-08 12:36:44 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-08-14 08:37:38 +0200 |
| commit | 49043cbad1db2e97daffe54d5ee32103c11dd4fd (patch) | |
| tree | 8bcf19d4634c6ab93278d00323548486e02254c7 /arch/arm/cpu/armv7/sunxi | |
| parent | fbf10ae98657f1a888b670078f4eb18f9172c834 (diff) | |
| download | u-boot-imx-49043cbad1db2e97daffe54d5ee32103c11dd4fd.zip u-boot-imx-49043cbad1db2e97daffe54d5ee32103c11dd4fd.tar.gz u-boot-imx-49043cbad1db2e97daffe54d5ee32103c11dd4fd.tar.bz2 | |
sunxi: clock: Add clock_get_pll3() helper function
Add a helper function to get the pll3 clock rate.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/cpu/armv7/sunxi')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 9 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 12 |
2 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index c3e04af..7c8eff9 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -198,6 +198,15 @@ void clock_set_pll3(unsigned int clk) CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg); } +unsigned int clock_get_pll3(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll3_cfg); + int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT); + return 3000000 * m; +} + unsigned int clock_get_pll5p(void) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 3bfa122..1d6f839 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -188,6 +188,18 @@ void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) } #endif +unsigned int clock_get_pll3(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll3_cfg); + int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1; + int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1; + + /* Multiply by 1000 after dividing by m to avoid integer overflows */ + return (24000 * n / m) * 1000; +} + unsigned int clock_get_pll6(void) { struct sunxi_ccm_reg *const ccm = |