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* arm: omap4: Fix SDRAM AUTO DETECTIONLokesh Vutla2013-04-08-1/+0
| | | | | | | | | | | | | | Commit "8602114 omap: emif: configure emif only when required" breaks SDRAM_AUTO_DETECTION. The issue is dmm_init() depends on emif_sizes[](SDRAM Auto detection) done in do_sdram_init(). The above commit moves dmm_init() above do_sdram_init() because of which dmm_init() uses uninitialized emif_sizes[]. So instead of using global emif_sizes[], get sdram details locally and calculate emif sizes. Reported-by: Michael Cashwell <mboards@prograde.net> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: dra7xx: Add silicon id support for DRA752 socLokesh Vutla2013-03-11-0/+3
| | | | | | | | Adding CPU detection support for the DRA752 ES1.0 soc. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: Add DDR related data for DRA752 ES1.0Lokesh Vutla2013-03-11-2/+25
| | | | | | | | | | DRA752 uses DDR3. Populating the corresponding structures with DDR3 data. Writing into MA registers if only MA is present in that soc. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: Add control module changesLokesh Vutla2013-03-11-2/+75
| | | | | | | | | | Control module register addresses are changed from OMAP5 to DRA7XX socs. So adding the necessary changes for the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: clock: Add the dplls dataLokesh Vutla2013-03-11-3/+61
| | | | | | | | | | | | A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: clock: Add the prcm changesLokesh Vutla2013-03-11-5/+234
| | | | | | | | PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX. So adding the necessary register changes for DRA7XX socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP5: srcomp: enable slew rate compensation cells after powerupLokesh Vutla2013-03-11-1/+120
| | | | | | | | | | | | | | After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCsLokesh Vutla2013-03-11-2/+87
| | | | | | | | | | | | | Add pre calculated timing settings of LPDDR2 and DDR3 memories present in OMAP5430 and OMAP5432 ES2.0 versions. Also adding the DDR pad io settings required for OMAP543X SOCs here. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendumSRICHARAN R2013-03-11-99/+136
| | | | | | | | | | | | | | | | | Change OPP settings as per the latest 0.5 version of addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched here to add dummy dividers. While here correcting OPP_NOM mpu, core frequency for OMAP4430 ES2.x Note that OMAP5430 ES1.0 support is still kept alive and would be removed in a cleanup later. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
* ARM: OMAP5: clock: Add the prcm register changes required for ES2.0SRICHARAN R2013-03-11-0/+288
| | | | | | | | | | | PRCM register addresses are changed from ES1.0 to ES2.0 due to PER power domain getting moved to CORE power domain. So adding the nessecary register changes for the same. Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* ARM: OMAP5: Add silicon id support for ES2.0 revision.SRICHARAN R2013-03-11-11/+16
| | | | | | | | | Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
* ARM: OMAP5: Clean up iosettings codeLokesh Vutla2013-03-11-44/+67
| | | | | | | | | | | There is some code duplication in the ddr io settings code. This is avoided by moving the data to a Soc specific place and letting the code generic. This avoids unnessecary code addition for future socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Make control module register structure genericLokesh Vutla2013-03-11-56/+124
| | | | | | | | | | | | A seperate omap_sys_ctrl_regs structure is defined for omap4 & 5. If there is any change in control module for any of the ES versions, a new structure needs to be created. In order to remove this dependency, making the register structure generic for all the omap4+ boards. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Cleanup emif specific filesLokesh Vutla2013-03-11-42/+77
| | | | | | | | | | | | Removing the duplicated code in ddr3 initialization. Also creating structure for lpddr2 mode registers to avoid unnessecary revision checks. These change reduces code addition for future Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Clean up the pmic codeSRICHARAN R2013-03-11-99/+43
| | | | | | | | | | The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Cleanup the clocks layerSRICHARAN R2013-03-11-396/+355
| | | | | | | | | | | | | | | Currently there is quite a lot of code which is duplicated in the clocks code for OMAP 4 and 5 Socs. Avoiding this here by moving the clocks data to a SOC specific place and the sharing the common code. This helps in addition of a new Soc with minimal changes. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Change the PRCM structure prototype common for all SocsSRICHARAN R2013-03-11-108/+453
| | | | | | | | | | | | The current PRCM structure prototype directly matches the hardware register layout. So there is a need to change this for every new silicon revision which has register space changes. Avoiding this by making the prototye generic and populating the register addresses seperately for all Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP4+: emif: Detect SDRAM from SDRAM config registerLokesh Vutla2013-03-11-2/+3
| | | | | | | | | | | Now SDRAM initialization is done on the basis of omap revision. Instead this should be done on basis of SDRAM type read from EMIF_SDRAM_CONFIG register. This will be helpful to avoid unnessecary cpu checks for new boards Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4/5: Move USB clocks to essential group.SRICHARAN R2012-07-07-3/+3
| | | | | | | | | USB clocks will be required for fastboot, tftp related functionalities. Move these clocks to essential group inorder to have the functionality working when non-essential clocks are not enabled. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4/5: Move gpmc clocks to essential group.SRICHARAN R2012-07-07-1/+1
| | | | | | | | | | GPMC clocks are currently getting enabled as a part non-essential clocks. This will be required during NOR boot. Move this to essential group to keep the functionality, when non-essential clocks are not enabled. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4+: Move external phy initialisations to arch specific place.SRICHARAN R2012-07-07-0/+31
| | | | | | | | | | The external phy is present in the case OMAP5 soc is currently configured in emif-common.c. This results in having dummy structures for those Socs which do not have a external phy. So by having a weak function in emif-common and overriding it in OMAP5, avoids the use of dummy structures. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: Change voltages for omap5432Lokesh Vutla2012-07-07-10/+21
| | | | | | Change voltages for OMAP5432 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: EMIF: Add support for DDR3 deviceLokesh Vutla2012-07-07-0/+15
| | | | | | | | | In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: ADD precalculated timings for ddr3Lokesh Vutla2012-07-07-1/+49
| | | | | | | Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: Configure the io settings for omap5432 uevm boardLokesh Vutla2012-07-07-19/+79
| | | | | | This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: ADD chip detection for OMAP5432 SOCLokesh Vutla2012-07-07-1/+9
| | | | | | This patch adds chip detection for OMAP5432 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP5: dmm: Create a tiler trap section.SRICHARAN R2012-07-07-3/+3
| | | | | | | | | | | | | | | | | The unmapped entries in tiler space are set with values 0xFF. So creating a DMM section of size 16MB at 0xFF000000 with ADDRSPACE set to 0x2. This way all the unmapped entry accesses to tiler will be trapped by the EMIF and a error response is sent to the L3 interconnect. L3 errors are inturn reported to MPU. Note that here the tiler trap section is overlapping with the actual ddr physical space and we lose 16MB out of the total 2GB. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: reset: Use cold reset in case of 5430ES1.0SRICHARAN R2012-05-15-0/+14
| | | | | | | | Warm reset is not functional in case of omap5430ES1.0. So override the weak reset_cpu function to use cold reset instead. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: ddr: Change the ddr device name.SRICHARAN R2012-05-15-16/+16
| | | | | | | The ddr part name used in OMAP5 ES1.0 soc is a SAMSUNG part and not a ELPIDA part. So change this. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP4/5: Make the sysctrl structure commonSRICHARAN R2012-05-15-2/+2
| | | | | | | | | Make the sysctrl structure common, so that it can be used in generic functions across socs. Also change the base address of the system control module, to include all the registers and not simply the io regs. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP4/5: Make the silicon revision variable common.SRICHARAN R2012-05-15-3/+3
| | | | | | | | The different silicon revision variable names was defined for OMAP4 and OMAP5 socs. Making the variable common so that some code can be made generic. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: hwinit: Add the missing break statementSRICHARAN R2012-05-15-0/+1
| | | | | | | The break statement is missing in init_omap_revision function, resulting in a wrong revision identification. So fixing this. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: palmas: Configure nominal opp vdd valuesSRICHARAN R2012-05-15-9/+23
| | | | | | | | | | | The nominal opp vdd values as recommended for ES1.0 silicon is set for mpu, core, mm domains using palmas. Also used the right sequence to enable the vcores as per a previous patch from Nishant Menon, which can be dropped now. http://lists.denx.de/pipermail/u-boot/2012-March/119151.html Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.SRICHARAN R2012-05-15-19/+62
| | | | | | | | | The OMAP5 silicon has new DDR PHY design, which includes a external PHY as well. So configuring the ext PHY parameters here. Also the EMIF timimg registers and a couple of DDR mode registers needs to be updated based on the testing from the actual silicon. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: io: Configure the io settings for omap5430 sevm board.SRICHARAN R2012-05-15-0/+83
| | | | | | | | | The control module provides options to set various signal integrity parameters like the output impedance, slew rate, load capacitance for different pad groups. Configure these as required for the omap5430 sevm board. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: clocks: Change clock settings as required for ES1.0 silicon.SRICHARAN R2012-05-15-36/+73
| | | | | | | | Aligning all the clock related settings like the dpll frequencies, their respective clock outputs, etc to the ideal values recommended for OMAP5430 ES1.0 silicon. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP4460: TPS Ensure SET1 is selected after voltage configurationNishanth Menon2012-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms. Currently we control this pin with a mux configuration as part of boot sequence. Current configuration results in the following voltage waveform: |---------------| (SET1 default 1.4V) | --------(programmed voltage) | <- (This switch happens on mux7,pullup) vdd_mpu(TPS) -----/ (OPP boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -----------------------/ (OPP boot voltage) Problem 1) |<----- Tx ------>| timing violation for a duration Tx close to few milliseconds. Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP. By using GPIO as recommended as standard procedure by TI, the sequence changes to: -------- (programmed voltage) vdd_mpu(TPS) ------------/ (Opp boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -------------/ (OPP boot voltage) NOTE: This does not attempt to address OMAP5 - Aneesh please confirm Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP3+: Introduce generic logic for OMAP voltage controllerNishanth Menon2012-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | OMAP Voltage controller is used to generically talk to PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code in multiple SoC code, introduce a common voltage controller logic which can be re-used from elsewhere. With this change, we replace setup_sri2c with omap_vc_init which has the same functionality, and replace the voltage scale replication in do_scale_vcore and do_scale_tps62361 with omap_vc_bypass_send_value. omap_vc_bypass_send_value can also now be used with any configuration of PMIC. NOTE: Voltage controller controlling I2C_SR is a write-only data path, so no register read operation can be implemented. Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* omap4/5: Add support for booting with CH.Sricharan2011-11-15-10/+30
| | | | | | | | | | | | | | | | Configuration header(CH) is 512 byte header attached to an OMAP boot image that will help ROM code to initialize clocks, SDRAM etc and copy U-Boot directly into SDRAM. CH can help us in by-passing SPL and directly boot U-boot, hence it's an alternative for SPL. However, we intend to support both CH and SPL for OMAP4/5. Initialization done through CH is limited and is not equivalent to that done by SPL. So U-Boot has to distinguish between the two cases and handle them accordingly. This patch takes care of doing this. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap5: emif: Add emif/ddr configurations required for omap5 evmSricharan2011-11-15-0/+283
| | | | | | | | | | | | | Add the emif configurations required for omap5 soc.Add the correct ddr part configurations required for omap5 evm board. EDB8164B3PH from ELPIDA is the part used on the board. Also changes are done to retain some part of the code common for OMAP4/5 and keep only the remaining in the Soc specific directories. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap5: clocks: Add clocks support for omap5 platform.Sricharan2011-11-15-0/+412
| | | | | | | | | | | | Adding the correct configurations required for dplls, clocks, for omap5 Soc. Also changes are done to retain some part of the code common for OMAP4/5 and move only the remaining to the Soc specific directories. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap5: Add minimal support for omap5430.Sricharan2011-11-15-0/+154
This patch adds the minimal support for OMAP5. The platform and machine specific headers and sources updated for OMAP5430. OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Also moved some part of code from the basic platform support that can be made common for OMAP4/5. Rest is kept out seperately. The same approach is followed for clocks and emif support in the subsequent patches. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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