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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-02-12 21:29:07 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-11 11:06:11 -0400 |
| commit | 7831419d7bd9cf61a53ad6f7f23dae107812fdf5 (patch) | |
| tree | 339338c4d16d2e0c74ed77938b00e017d935e488 /arch/arm/cpu/armv7/omap5 | |
| parent | 8b12f1779e339e375151883b3d0aadbd4fdce894 (diff) | |
| download | u-boot-imx-7831419d7bd9cf61a53ad6f7f23dae107812fdf5.zip u-boot-imx-7831419d7bd9cf61a53ad6f7f23dae107812fdf5.tar.gz u-boot-imx-7831419d7bd9cf61a53ad6f7f23dae107812fdf5.tar.bz2 | |
arm: dra7xx: Add DDR related data for DRA752 ES1.0
DRA752 uses DDR3. Populating the corresponding structures
with DDR3 data.
Writing into MA registers if only MA is present in that soc.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/sdram.c | 26 |
2 files changed, 25 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 7f1808c..ced274e 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -586,6 +586,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) *regs = &ioregs_omap5432_es1; break; case OMAP5432_ES2_0: + case DRA752_ES1_0: *regs = &ioregs_omap5432_es2; break; diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 2ef7fcd..6b461e4 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -155,7 +155,16 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, .dmm_lisa_map_2 = 0x80740300, - .dmm_lisa_map_3 = 0xFF020100 + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +const struct dmm_lisa_map_regs lisa_map_512M_x_1 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x0, + .dmm_lisa_map_3 = 0x80500100, + .is_ma_present = 0x1 }; static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) @@ -171,6 +180,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_532_mhz_2cs_es2; break; case OMAP5432_ES2_0: + case DRA752_ES1_0: default: *regs = &emif_regs_ddr3_532_mhz_1cs_es2; } @@ -182,7 +192,18 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs **dmm_lisa_regs) { - *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; + switch (omap_revision()) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + case OMAP5432_ES1_0: + case OMAP5432_ES2_0: + *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; + break; + case DRA752_ES1_0: + default: + *dmm_lisa_regs = &lisa_map_512M_x_1; + } + } void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) @@ -297,6 +318,7 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) *regs = ddr3_ext_phy_ctrl_const_base_es1; break; case OMAP5432_ES2_0: + case DRA752_ES1_0: default: *regs = ddr3_ext_phy_ctrl_const_base_es2; |