Commit message (Expand) | Author | Age | Lines | |
---|---|---|---|---|
* | Exynos5: ddr3: Choose between single or double channel config | Akshay Saraswat | 2014-11-17 | -0/+10 |
* | DMC: Exynos5: Enable update mode for DREX controller | Alim Akhtar | 2014-11-17 | -0/+19 |
* | Exynos5420: DMC: Add software read leveling | Akshay Saraswat | 2014-06-13 | -4/+246 |
* | DMC: exynos5420: Gate CLKM to when reading PHY_CON13 | Doug Anderson | 2014-06-13 | -5/+38 |
* | Exynos5420: Remove code for enabling read leveling | Akshay Saraswat | 2014-06-13 | -71/+0 |
* | Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_init | Akshay Saraswat | 2014-06-13 | -5/+2 |
* | Exynos5420: Add DDR3 initialization for 5420 | Rajeshwari Birje | 2013-12-30 | -10/+429 |
* | Add GPL-2.0+ SPDX-License-Identifier to source files | Wolfgang Denk | 2013-07-24 | -17/+1 |
* | EXYNOS: Move files from board/samsung to arch/arm | Rajeshwari Shinde | 2013-07-05 | -0/+233 |