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* lcd: Fix compile warning in 64bit modeAlexander Graf2016-03-27-2/+2
| | | | | | | | When compiling the code for 64bit, the lcd code emits warnings because it tries to cast pointers to 32bit values. Fix it by casting them to longs instead, actually properly aligning with the function prototype. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm: Add support for HYP mode and LPAE page tablesAlexander Graf2016-03-27-12/+161
| | | | | | | | | | | | | | We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Add 32bit arm compatible dcache definitionsAlexander Graf2016-03-27-1/+5
| | | | | | | | | | | We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de>
* board: ti: DRA7: Add DRA72-rev C evm pinmuxNishanth Menon2016-03-27-36/+110
| | | | | | | | | | | | Add the pinmux data for rev C evm. This is different from previous revisions of the platform thanks to the deltas introduced both from silicon side and from SoC side. Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for SR2.0 silicon. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5/DRA7: Expose do_set_iodelayNishanth Menon2016-03-27-2/+4
| | | | | | | | do_set_iodelay can now be used from board files based on needs of the platforms variation they have. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5/DRA7: Split iodelay functionality into sub stepsNishanth Menon2016-03-27-14/+52
| | | | | | | | | | | | | | | | Since many platforms may need different pad configuration required depending on variation of the platform with minor deltas, it is easier to maintain a sub step based approach to allow for pin mux and iodelay configuration which may depend on the platform variations and need to be done in IO isolation. While we retain the older __recalibrate_iodelay function which provides a ready sequencing, __recalibrate_iodelay_start and __recalibrate_iodelay_end may be alternatively used now and the callers will be responsible for the correct sequencing of operations. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ti: DRA72: revC evm: Update sdram timing configuration for SR2.0Ravi Babu2016-03-27-4/+55
| | | | | | | | | | | | | | | DDR configuration has changes from SR1.1 based Rev-A/B version of evm to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB. Update the DDR configuration based on data from EMIF configuration tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the configuration. Tested-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72: sdram: Update sdram ext phy configuration for SR2.0Nishanth Menon2016-03-27-1/+43
| | | | | | | Based on data from EMIF configuration tool 1.1.1. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: hwdata: Update ioreg data for DRA72 SR2.0Nishanth Menon2016-03-27-1/+15
| | | | | | | | | Based on data from EMIF configuration tool 1.1.1. Expected update for CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has been incorporated as well. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA72x: Add support for detection of SR2.0Ravi Babu2016-03-27-0/+9
| | | | | | | | | Add support for detection of SR2.0 version of DRA72x family of processors. Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* efi_loader: Add GOP supportAlexander Graf2016-03-27-0/+205
| | | | | | | | | | | | The EFI standard defines a simple boot protocol that an EFI payload can use to access video output. This patch adds support to expose exactly that one (and the mode already in use) as possible graphical configuration to an EFI payload. With this, I can successfully run grub2 with graphical output. Signed-off-by: Alexander Graf <agraf@suse.de>
* ARM: keystone2: Convert BOOT_SET_BITFIELD into static inline functionNishanth Menon2016-03-27-7/+11
| | | | | | | | | Fix up BOOT_SET_BITFIELD to be a static inline function to be readable with the same functionality. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Convert BOOT_READ_BITFIELD into static inline functionNishanth Menon2016-03-27-10/+15
| | | | | | | | | BOOT_READ_BITFIELD can easily be a static inline function and be a little more readable with the same functionality. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Convert BOOTBITMASK to static inline functionNishanth Menon2016-03-27-5/+9
| | | | | | | | | BOOTBITMASK is almost impossible to decode, so convert it into a simpler static line functions of equivalent solution. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* tools: env: fw_parse_script: simplify removal of newline/carriage returnAndreas Fenkart2016-03-26-6/+4
| | | | | | fgets returns when the first '\n' is found Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
* tools: env: split fw_string_blank into skip_chars / skip_blanksAndreas Fenkart2016-03-26-9/+14
| | | | Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
* tools: env: fw_string_blank: return from loop when item foundAndreas Fenkart2016-03-26-5/+2
| | | | Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
* tools: env: replace WHITESPACE macro by isblankAndreas Fenkart2016-03-26-4/+3
| | | | Signed-off-by: Andreas Fenkart <andreas.fenkart@digitalstrom.com>
* stm32f746-disco: enable flash supportVikas Manocha2016-03-26-7/+10
| | | | | | This patch enables embedded flash for stm32f746 discovery board. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* stm32: stm32f4: move flash driver to mtd driver locationVikas Manocha2016-03-26-50/+59
| | | | | | | Same flash driver can be used by other stm32 families like stm32f7. Better place for this driver would be mtd driver location. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* usb: gadget: Move CONFIG_USB_GADGET to KconfigSam Protsenko2016-03-25-41/+222
| | | | | | | | | | | | | | The description was borrowed from kernel. "tristate" type was changed to "bool" (I believe we don't support modules for u-boot yet, right?). CONFIG_USB_GADGET requires CONFIG_USB to be defined too, so add it along as well. Definitions were added to defconfig files in a way that "make savedefconfig" generates exactly the same file as used defconfig. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> [trini: Add zynq_zc702 conversion] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-03-25-26/+507
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| * tools: kwboot: Add xmodem timeout optionKevin Smith2016-03-24-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | Add command-line specification of xmodem timeout. If the binary header needs to take a while to do something (e.g. DDR ECC scrubbing), the xmodem transfer can time out. Add a configurable xmodem block timeout to allow transfers with slow binary headers to succeed. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * tools: kwboot: Clean up usage textKevin Smith2016-03-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | Usage text was getting unwieldy and somewhat incorrect. The usage summary implied that some options were mutually exclusive (e.g. -q or -s). Clean up the summary to just include the important ones, and include a generic "[OPTIONS]" instead. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: db-88f6820: Drop obsolete binary.0 placeholderAndreas Färber2016-03-24-16/+0
| | | | | | | | | | | | | | | | | | | | It has been superseded in kwbimage.cfg in favor of an SPL in commit 9e30b31d20f0b793465d07f056b3d9885f578c0d (arm: mvebu: db-88f6820: Add SPL support with DDR init code). Found via code review. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: theadorable: Add StratixV FPGA programming supportStefan Roese2016-03-24-2/+234
| | | | | | | | | | | | | | | | | | | | This patch adds support for Altera StratixV bitstream programming. 2 FPGAs are connected to the SPI busses. This patch uses board specific write code to program the bitstream via SPI direct write mode. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: spi.h: Add registers for direct write accessStefan Roese2016-03-24-0/+3
| | | | | | | | | | | | | | | | | | The direct write config register is needed for SPI direct write mode configuration. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: Add some SPI CS attributesStefan Roese2016-03-24-0/+3
| | | | | | | | | | | | | | | | | | | | These attribute defines may be used to map an area of memory for direct access to the specific SPI devices. See SPI Direct Access Mode for further information. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
| * fpga: altera: Add StratixV supportStefan Roese2016-03-24-0/+127
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for programming of the StratixV FPGAs. Programming is done in this case (board theadorable) via SPI. The board may provide board specific code for bitstream programming. This StratixV support will be used by the theadorable board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * gpio: Add DM GPIO driver for Marvell MVEBUStefan Roese2016-03-24-0/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a DM GPIO driver for the Marvell MVEBU SoCs. There are other non-DM drivers that might be used on these platforms. But this patch creates a new DM driver. Which will be used by all Armada XP/38x boards. Other MVEBU SoC (Kirkwood / Orion) may follow once they support DM as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: Fix ddr3_init() cpu configDirk Eibach2016-03-24-2/+0
| | | | | | | | | | | | | | | | Armada 38x has a maximum of two cores. Probably copy/paste bug from Armada XP. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: sheevaplug: correct nand partition layoutPeter Korsgaard2016-03-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1e3d640316 (ARM: sheevaplug: redefine MTDPARTS) changed the partition layout (without any description why), but didn't change the offset/size to load the kernel from or the root=/dev/mtdblockX in the bootargs. The 3MB forseen for a kernel is furthermore too little. A 4.4 build of mvebu_v5_defconfig is 3.6MB: -rw-r--r-- 1 peko peko 3.6M Jan 16 20:24 uImage.kirkwood-sheevaplug When device tree support for sheevaplug was added to the kernel in commit ee514b381e (ARM: Kirkwood: Add dts files for Sheevaplug and eSATA Sheevaplug) a default flash partition layout (used if mtdparts= isn't passed on the command line / CONFIG_MTD_CMDLINE_PARTS isn't enabled) with 1MB for u-boot / environment, 4MB for the kernel and the rest for the rootfs, so use that layout here and adjust the kernel loading to match. Signed-off-by: Peter Korsgaard <peter@korsgaard.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-03-23-1173/+6749
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| * sunxi: A83T: fix 32bit overflow warningvishnupatekar2016-03-23-1/+1
| | | | | | | | | | | | | | | | | | | | In mctl_channel_init, (0x50<<26) which overflows 32bit. It was supposed to be 0x50<<16,corrected now. Reported-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Select CONFIG_OF_BOARD_SETUP from arch/arm/KconfigHans de Goede2016-03-23-76/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Always select OF_BOARD_SETUP on sunxi, rather then having it in almost all our defconfigs. This also fixes it missing from some recently added defconfigs. This commit also modifies our ft_board_setup() to not cause warnings when CONFIG_VIDEO_DT_SIMPLEFB is not set, since we will now always build it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: sinovoip-bpi-m3: drop LDO settings from defconfigvishnupatekar2016-03-23-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Kconfig default settings are same as mentioned Sinovoip Bpi-m3 schematic. As axp818 ALDO support is enabled, it causes bpi-m3 fail to boot if ALDOs are set to 0. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Specify SATAPWR pin for Orangepi PlusHans de Goede2016-03-23-0/+1
| | | | | | | | | | | | | | This enables the use of the sata connector in u-boot. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Turn satapwr on from board_initHans de Goede2016-03-23-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 2 reasons for doing this: 1) The main reason for doing this is to move it outside of board/sunxi/ahci.c, so that it can be used on boards which use a usb<->sata chip too; 2) While doing this I realized that doing it from board_init also meant doing it much earlier. Some printf get_timer(0) calls show that the time between board_init() and scsi_init() is more then 600 ms, so we can drop the mdelay(500) While at it also drop the printf("SUNXI SCSI INIT\n") AHCI init is noisy enough by itself. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Fix gmac not working due to cpu_eth_init no longer being calledHans de Goede2016-03-23-41/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpu_eth_init is no longer called for dm enabled eth drivers, this was causing the sunxi gmac eth controller to no longer work in u-boot. This commit fixes this by calling the clock, reset and pinmux setup function from s_init() and enabling the phy power pin (if any) from board_init(). The enabling of phy power cannot be done from s_init because it uses dm and dm is not ready yet at this point. Note that the mdelay is dropped as the phy gets enabled much earlier now, so it is no longer needed. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Tested-by: Karsten Merker <merker@debian.org> Tested-by: Michael Haas <haas@computerlinguist.org>
| * sunxi: Fix 2nd usb controller on sun4i/sun7i no longer workingHans de Goede2016-03-23-5/+23
| | | | | | | | | | | | | | | | | | | | The 2nd usb controller on sun4i/sun7i has its base address 0x8000 bytes from the 1st one, rather then 0x1000. Also the ahb clk gates are interleaved with the ohci clk-gates introducing a hole between the clks for usb1 and usb2. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Enable support for the eMMC found on the orangepi plusHans de Goede2016-03-23-0/+2
| | | | | | | | | | | | | | This enables support for the eMMC found on the orangepi plus. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * spl: Print from which mmc slot spl is trying to bootHans de Goede2016-03-23-3/+3
| | | | | | | | | | | | | | | | | | | | On some sunxi boards (and presumably also non sunxi boards) u-boot can be either loaded from a sdcard in a micro-sd slot, or from eMMC. Print which MMC spl tries to boot from, to help debugging. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * sunxi: Add a bunch of missing compatible strings to sunxi_gpio.cHans de Goede2016-03-23-1/+14
| | | | | | | | | | | | | | | | | | | | | | The kernel has different compatible strings for the pio block because the pin-muxing is different on all the different SoCs, but sunxi_gpio.c only support the basic gpio functionality, which is identical everywhere. Add the missing compatible strings for various SoC models. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Specify USB vbus pins for orangepi boardsHans de Goede2016-03-23-0/+4
| | | | | | | | | | | | | | | | This fixes the USB ports not working on the orangepi_plus and stops us from messing with gpio-s which we should not touch on the orangepi_pc. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add support for USB vbus pin for USB3Hans de Goede2016-03-23-0/+7
| | | | | | | | | | | | | | The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Enable realtek phy supportHans de Goede2016-03-23-0/+1
| | | | | | | | | | | | | | | | Enable building of drivers/net/phy/realtek.c so that realtek phys get properly initialized. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Enable composite video out on the CHIPAlex Kaplan2016-03-23-0/+1
| | | | | | | | | | | | | | | | | | | | The CHIP has a composite video output in the mini-Jack connector, alongside with the 2 audio channels. Enable this output in U-Boot. Signed-off-by: Alex Kaplan <kaplan2539@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Fix DCDC2 output in CHIP_defconfigBoris Brezillon2016-03-23-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Unlike the datasheet recommendation, the R8 SoC requires a 1.4V supply for its CPU when operating at 1Ghz. Rely on the default value specified in the Kconfig entry. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Configure only LVDS pins instead of all LCD pins when LVDS interface ↵Lawrence Yu2016-03-23-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | selected The behavior before this patch would attempt to configure the mux setting for pins 0 to 27 on PORTD to all be setting 3 for LVDS. The LVDS interface actually only uses pins 18 to 27 and not pins 0 to 27 as in the parallel LCD interface. This patch restricts the configuration to only the relevant pins 18 to 27 on PORTD. This was tested on a sun8i A33 tablet with an LVDS screen. MMC1 has the capability to use pins 2 to 7 on PORTD and the mux on those pins was being inadvertently set to setting 3 for MMC functionality which this patch corrects. Signed-off-by: Lawrence Yu <lyu@micile.com> [hdegoede@redhat.com: Only apply this change to A23 / A33] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Support SID e-fuses on A83T and H3Chen-Yu Tsai2016-03-23-0/+7
| | | | | | | | | | | | | | | | | | | | On the A83T and H3, the SID block is at a different address. Furthurmore, the e-fuses are at an offset of 0x200 within the hardware's address space. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
generated by cgit v1.1 at 2024-11-06 15:25:55 +0000