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* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-09-18-1179/+1472
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| * | ARM: uniphier: update DRAM init code for LD20 SoCMasahiro Yamada2016-09-19-62/+447
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import the latest version from the Diag software. - Support LD21 SoC (including DDR chips in the package) - Per-board granule adjustment for both reference and TV boards - Misc cleanups Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: add PLL init code for LD20 SoCMasahiro Yamada2016-09-19-5/+234
| | | | | | | | | | | | | | | | | | | | | | | | Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: collect clock/PLL init code into a single directoryMasahiro Yamada2016-09-19-24/+18
| | | | | | | | | | | | | | | | | | | | | | | | Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory will be helpful when we want to share code between SPL and U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: move PLL init code to U-Boot proper where possibleMasahiro Yamada2016-09-19-495/+365
| | | | | | | | | | | | | | | | | | | | | | | | The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PERMasahiro Yamada2016-09-18-1/+1
| | | | | | | | | | | | | | | | | | Basically, this should not be configured by users. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20Masahiro Yamada2016-09-18-31/+10
| | | | | | | | | | | | | | | | | | | | | This is the last code in the mach-uniphier/pinctrl/ directory. Push the remaining code out to delete the directory entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20Masahiro Yamada2016-09-18-44/+5
| | | | | | | | | | | | | | | | | | | | | Use the pin-mux data in the pinctrl drivers by directly calling pinctrl_generic_set_state(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: dts: uniphier: include System Bus pin group node in SPL DTMasahiro Yamada2016-09-18-0/+8
| | | | | | | | | | | | | | | | | | | | | This will be needed for setting up the System Bus pin-mux via the LD11/LD20 pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: consolidate NAND pin-mux settingsMasahiro Yamada2016-09-18-274/+51
| | | | | | | | | | | | | | | | | | | | | | | | The NAND subsystem has not supported the Driver Model yet, but the NAND pin-mux data are already in the pinctrl drivers. Use them by calling pinctrl_generic_set_state() directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove ad-hoc pin-mux code for sLD3Masahiro Yamada2016-09-18-58/+0
| | | | | | | | | | | | | | | | | | These settings are nicely cared by the pinctrl driver now. Remove. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoCMasahiro Yamada2016-09-18-2/+0
| | | | | | | | | | | | | | | | | | This is enabled by default for all the supported boot modes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: select PINCTRL and SPL_PINCTRLMasahiro Yamada2016-09-18-10/+2
| | | | | | | | | | | | | | | | | | | | | Now all UniPhier SoCs support a pinctrl driver. Select (SPL_)PINCTRL since it is mandatory even for base use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: dts: uniphier: add pinctrl device node and pinctrl propertiesMasahiro Yamada2016-09-18-0/+43
| | | | | | | | | | | | | | | | | | DT-side updates to make pinctrl on sLD3 SoC really available. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add UniPhier sLD3 pinctrl driverMasahiro Yamada2016-09-18-0/+135
| | | | | | | | | | | | | | | | | | Add pin-mux support for UniPhier sLD3 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: support 4bit-width pin-mux register capabilityMasahiro Yamada2016-09-18-14/+11
| | | | | | | | | | | | | | | | | | | | | On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit wide on sLD3 SoC. Support it for the sLD3 pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: introduce flags to adjust DRAM timing for LD20/LD21Masahiro Yamada2016-09-17-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately, this SoC needs per-board adjustment between clock and address/command lines. This flag will be passed to the DRAM init function and used for compensating the difference of DRAM timing parameters. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: fix DRAM size of LD21 SoC packageMasahiro Yamada2016-09-17-1/+1
| | | | | | | | | | | | | | | | | | The channel 0 DRAM size of LD21 is half of that of LD20. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: merge board init functions into board_init()Masahiro Yamada2016-09-14-42/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the UniPhier platform calls several init functions in the following order: [1] spl_board_init() [2] board_early_init_f() [3] board_init() [4] board_early_init_r() [5] board_late_init() The serial console is not ready at the point of [2], so we want to avoid using [2] from the view point of debuggability. Fortunately, all of the initialization in [2] can be delayed until [3]. I see no good reason to split into [3] and [4]. So, merge [2] through [4]. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: use checkboard() instead of misc_init_f()Masahiro Yamada2016-09-14-25/+7
| | | | | | | | | | | | | | | | | | | | | We can use checkboard() stub to show additional board information, so misc_init_f() should not be used for this purpose. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove IECTRL setup code of LD4 SoCMasahiro Yamada2016-09-14-6/+0
| | | | | | | | | | | | | | | | | | This should be handled by the pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: move register base macros from header to .c fileMasahiro Yamada2016-09-14-4/+4
| | | | | | | | | | | | | | | | | | | | | These macros are only referenced in pinctrl-uniphier-core.c, so they need not reside in a header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | pinctrl: uniphier: add System Bus pin-mux settingsMasahiro Yamada2016-09-14-0/+147
| | | | | | | | | | | | | | | | | | This is needed to get access to UniPhier System Bus (external bus). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: uniphier-sd: migrate to CONFIG_BLKMasahiro Yamada2016-09-14-26/+26
| | | | | | | | | | | | | | | | | | | | | This is the state-of-the-art MMC driver implementation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | ARM: uniphier: enable Generic EHCI driver for Pro4 SoCMasahiro Yamada2016-09-14-0/+2
| | | | | | | | | | | | | | | | | | | | | This SoC is equipped with two EHCI cores and two xHCI cores. Enable the generic EHCI driver for the former. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: delete unnecessary xHCI pin-mux settingsMasahiro Yamada2016-09-14-48/+0
| | | | | | | | | | | | | | | | | | | | | These ad-hoc pinmux settings were used for the legacy xHCI driver, which has gone now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | usb: uniphier: remove UniPhier xHCI driver and select DM_USBMasahiro Yamada2016-09-14-97/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver has not been converted to Driver Model, and it is an obstacle to migrate other block device drivers. Remove it for now. The UniPhier SoCs already use a DM-based EHCI driver, so now ARCH_UNIPHIER can select DM_USB. These two changes must be done atomically because removing the legacy driver causes a build error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | ARM: uniphier: sort select:s alphabeticallyMasahiro Yamada2016-09-14-7/+7
| |/ | | | | | | | | | | | | ARCH_UNIPHIER is having more and more select:s. Sort them in case a select is accidentally duplicated. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-sunxiTom Rini2016-09-18-34/+209
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| * | sunxi: Enable USB gadget support for Sinlinx SinA33Chen-Yu Tsai2016-09-18-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sinlinx SinA33 has a USB OTG port, but VBUS is controlled manually from a jumper pad. Enable OTG in gadget mode, as well as the download gadget and related functions. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Enable USB host support for Sinlinx SinA33Chen-Yu Tsai2016-09-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sinlinx SinA33 has 1 USB host port. Enable EHCI_HCD support for it. Also enable USB mass storage support so we can access USB sticks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add mmc0 card detect pin for Sinlinx SinA33Chen-Yu Tsai2016-09-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Sinlinx SinA33 uses PB4 for mmc0 card detect. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add defconfig and dts for the NanoPi NEOJelle van der Waa2016-09-18-1/+148
| | | | | | | | | | | | | | | | | | | | | | | | | | | The NanoPi NEO is a simple h3 board with 512MB RAM, ethernet, one usb and one usb OTG connector. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: musb: Re-init musb controller on repeated probe callsHans de Goede2016-09-18-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With sunxi-musb musb_lowlevel_init() can fail when a charger; or no cable is plugged into the otg port. To avoid leaking the struct musb allocated by musb_init_controller() on repeated musb_usb_probe() calls, we were caching its result. But musb_init_controller() does more, such as calling sunxi_musb_init() which enables the clocks. Not calling sunxi_musb_init() causes the musb controller to stop working after a "usb reset" since that calls musb_usb_remove() which disables the clocks. This commit fixes this by removing the caching of the struct returned from musb_init_controller(), it replaces this by free-ing the allocated memory in musb_usb_remove() and calling musb_usb_remove() on musb_usb_probe() errors to ensure proper cleanup. While at it also make musb_usb_probe() and musb_usb_remove() static. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: musb: Power off OTG port VBUS when disabledChen-Yu Tsai2016-09-17-24/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux kernel musb driver expects VBUS to be off while initializing musb. Having it on results in a repeating string of warnings, followed by an unusable peripheral. The peripheral is only usable after physically removing the OTG adapter, letting musb reset its state. This partially reverts commit c9f8947e6604 ("sunxi: usb-phy: Never power off the usb ports") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: axp2xx: disable ldoio0/1 at bootHans de Goede2016-09-17-0/+28
| |/ | | | | | | | | | | | | | | | | | | When cold-booting the ldoio0/1 regulators are always off / the gpios are always at tristate. But when re-booting from android these are sometimes on. Disable them at axp_init time (iow as early as possible) to remove this difference between a cold boot and a reboot. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-arcTom Rini2016-09-18-3/+3
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| * | arc: Use -mcpu=XXX instead of obsolete -marcXXXAlexey Brodkin2016-09-16-3/+3
| |/ | | | | | | | | | | | | With newer ARC tools old way of CPU specification gets obsolete, so we're switching to newer and more common way of setting "-mcpu". Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Makefile: Give a build error if ad-hoc CONFIG options are addedSimon Glass2016-09-16-1/+64
| | | | | | | | | | | | | | | | | | New CONFIG options should be added via Kconfig. To help prevent new ad-hoc CONFIGs from being added, give a build error when these are detected. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | Kconfig: Add a whitelist of ad-hoc CONFIG optionsSimon Glass2016-09-16-0/+8471
| | | | | | | | | | | | | | Add a list of ad-hoc CONFIG options that don't use Kconfig. This can be used to check that new ones are not being added. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_YMODEM_SUPPORT to KconfigSimon Glass2016-09-16-20/+34
| | | | | | | | | | | | | | | | Convert CONFIG_SPL_YMODEM_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_WATCHDOG_SUPPORT to KconfigSimon Glass2016-09-16-14/+62
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_USB_SUPPORT to KconfigSimon Glass2016-09-16-3/+1
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_USB_HOST_SUPPORT to KconfigSimon Glass2016-09-16-1/+2
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_USBETH_SUPPORT to KconfigSimon Glass2016-09-16-1/+2
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_SPI_SUPPORT to KconfigSimon Glass2016-09-16-50/+78
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_SPI_FLASH_SUPPORT to KconfigSimon Glass2016-09-16-45/+81
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_SERIAL_SUPPORT to KconfigSimon Glass2016-09-16-172/+331
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_SATA_SUPPORT to KconfigSimon Glass2016-09-16-1/+1
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_POWER_SUPPORT to KconfigSimon Glass2016-09-16-47/+47
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-09 01:47:24 +0000