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authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-09-17 03:32:58 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2016-09-18 23:10:11 +0900
commitbbb119800f5ce8a291d707fd1a8e753959a93fd1 (patch)
tree1dbbd803c23aa81aa1d9214e0d20730bcab04e80
parentf6bbec3d5c12457e2ce207f662e65e7da70254ce (diff)
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pinctrl: uniphier: support 4bit-width pin-mux register capability
On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit wide on sLD3 SoC. Support it for the sLD3 pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-core.c20
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier.h5
2 files changed, 11 insertions, 14 deletions
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index f2fe313..51144b8 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -105,8 +105,10 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
int muxval)
{
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
- unsigned mux_bits, reg_stride, reg, reg_end, shift, mask;
- bool load_pinctrl;
+ unsigned reg, reg_end, shift, mask;
+ unsigned mux_bits = 8;
+ unsigned reg_stride = 4;
+ bool load_pinctrl = false;
u32 tmp;
/* some pins need input-enabling */
@@ -115,24 +117,18 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
if (muxval < 0)
return; /* dedicated pin; nothing to do for pin-mux */
+ if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_MUX_4BIT)
+ mux_bits = 4;
+
if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
/*
* Mode offset bit
* Normal 4 * n shift+3:shift
* Debug 4 * n shift+7:shift+4
*/
- mux_bits = 4;
+ mux_bits /= 2;
reg_stride = 8;
load_pinctrl = true;
- } else {
- /*
- * Mode offset bit
- * Normal 8 * n shift+3:shift
- * Debug 8 * n + 4 shift+3:shift
- */
- mux_bits = 8;
- reg_stride = 4;
- load_pinctrl = false;
}
reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index 76ea1be..5c3db2a 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -67,8 +67,9 @@ struct uniphier_pinctrl_socdata {
const char * const *functions;
int functions_count;
unsigned caps;
-#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1)
-#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
+#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(2)
+#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(1)
+#define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0)
};
#define UNIPHIER_PINCTRL_PIN(a, b) \