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* | ARM64: zynqmp: change sdhci compatible string.Sai Krishna Potthuri2016-11-15-2/+9
| | | | | | | | | | | | | | | | This patch changes the compatible string for sdhci node, adds "xlnx,device_id" and "xlnx,mio_bank" property to sdhci node. Signed-off-by: Sai Krishna Potthuri <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: List all SMMU idsMichal Simek2016-11-15-1/+72
| | | | | | | | | | | | Add SMMU description for all tested IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add support for zynqmp fpga managerNava kishore Manne2016-11-15-0/+4
| | | | | | | | | | | | | | Add support for zynqmp fpga manager. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add cortexa53 edac nodeNaga Sureshkumar Relli2016-11-15-0/+4
| | | | | | | | | | | | | | | | This patch adds edac node for arm cortexa53 to report errors on L1 and L2 caches. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Revert "ARM64: zynqmp: Add serdes address space dp driver"Michal Simek2016-11-15-2/+1
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 786db82bd5bf09cc8f78c8b14445e843d7566b1c. Since we are using serdes driver , no need of mapping serdes register space into DP driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: drm: Add DMA indexHyun Kwon2016-11-15-3/+5
| | | | | | | | | | | | | | | | Each plane can be associated with multiple DMA channels. So add index for each DMA channel. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Sync gpio node propertiesMichal Simek2016-11-15-2/+2
| | | | | | | | | | | | Keep dtsi in sync with mainline kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove xlnx,id propertyMichal Simek2016-11-15-16/+0
| | | | | | | | | | | | | | Remove unused xlnx,id property because it is not the part of DT binding. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: pci: Updating device tree as per upstreamBharat Kumar Gogada2016-11-15-1/+4
| | | | | | | | | | | | | | | | Updating required device tree changes as per mainlined driver from 4.6 kernel. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Support for multiple PM IDs assigned to a PM domainFilip Drazic2016-11-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, it was assumed that there is a 1:1 mapping between PM ID defined in the platform firmware and a PM domain. However, there can be a situation where multiple PM IDs belong to a single PM domain (e.g. PM IDs for GPU and two pixel processors correspond to a single PM domain). This patch adds support for assigning more than one PM ID to a single PM domain. Updated documentation accordingly. Assigned pixel processors PM IDs to GPU PM domain. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Add PM domains for GPU and PCIEFilip Drazic2016-11-15-0/+12
| | | | | | | | | | | | Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Remove unused PM domains for PLLFilip Drazic2016-11-15-25/+0
| | | | | | | | | | | | Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Remove unused DDR PM domainFilip Drazic2016-11-15-5/+0
| | | | | | | | | | | | | | | | | | | | DDR power states are handled by the PM firmware, so this domain is redundant. Also, since there is no device using this PM domain, it will be powered off during boot, which is wrong. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove note about level shifter on zcu102Michal Simek2016-11-15-1/+1
| | | | | | | | | | | | i2c device is just level shifter. Remove reference from dts. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add dcc port to dtsiMichal Simek2016-11-15-0/+11
| | | | | | | | | | | | | | | | Add dcc to dtsi for supporting system without serial port. DCC is enabled by default on ZynqMP. Adding dcc to zcu100 and zcu102 which were tested. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add gpio-keys for zcu102Michal Simek2016-11-15-0/+15
| | | | | | | | | | | | | | There is gpio push button on MIO22. Add it to DTS to have full board description. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Enable gpio-led as heartbeat on zcu102Michal Simek2016-11-15-0/+9
| | | | | | | | | | | | Show user that Linux is alive on the board. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Enable can1 for ep108Naga Sureshkumar Relli2016-11-15-0/+8
| | | | | | | | | | | | | | | | This patch enables can1 for ep108. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Added clocks to DT for ep108VNSL Durga2016-11-15-0/+44
| | | | | | | | | | | | | | Added clks for ep108 platform. Signed-off-by: VNSL Durga <vnsldurg@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add clocks for LPDDMAKedareswara rao Appana2016-11-15-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | Zynqmp DMA driver expects two clocks (main clock and apb clock) LPDDMA clock cofiguration is missing for the same in the zynqmp-clk.dtsi file. This patch updates for the same. Reported-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove DTC 1.4.2 warningsMichal Simek2016-11-15-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba/usb@fe200000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/usb@fe300000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video2channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-graphicschannel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name This patch is fixing them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Remove DTC 1.4.2 warningsMichal Simek2016-11-15-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property This patch is fixing them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Correct the sdhci minimum frequency for ep108Siva Durga Prasad Paladugu2016-11-15-1/+1
| | | | | | | | | | | | | | | | Correct the sdhci minimum frequency for ep platform. It should be right shift instead of left shift operand. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Ignore warnings from autogenerated filesMichal Simek2016-11-15-0/+12
| | | | | | | | | | | | | | | | Autogenerated files contain casting issues and missing function declaration and even usleep implementation. Suppress them for now till these files are fixed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Fix secondary bootmode enablingMichal Simek2016-11-15-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Do not setup use_alt bit which copy alternative boot mode to boot mode. The reason is that this bit is cleared after POR but not after any software reset which will cause that after SW reset bootrom will look for different boot image. This patch setups alternative boot mode selection (purely SW handling) and extends code to read this alternative boot mode first and use it if it is setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add support for SD1 with level shifters bootmodeSiva Durga Prasad Paladugu2016-11-15-0/+4
| | | | | | | | | | | | | | Add support for SD1 with level shifters bootmode. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Record board name as serial number for DFU/FASTBOOTMichal Simek2016-11-15-0/+4
| | | | | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Adjust to new SMC interface to get silicon versionSoren Brinkmann2016-11-15-0/+17
| | | | | | | | | | | | | | | | | | | | The new FW interface returns the IDCODE and version register, leaving extracting bitfields to the caller. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Add support for Zynq 7000S 7007s/7012s/7014s devicesMichal Simek2016-11-15-0/+30
| | | | | | | | | | | | | | Zynq 7000S (Single A9 core) devices is using different ID code. This patch adds this new codes and assign them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | net: zynq_gem: Correct SGMII enable bit settingSiva Durga Prasad Paladugu2016-11-15-1/+1
| | | | | | | | | | | | | | | | | | Correct the SGMII enable bit position to 27 instead of 31. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: zynq_gem: Modify the nwcfg bit definitionsSiva Durga Prasad Paladugu2016-11-15-8/+8
| | | | | | | | | | | | | | | | | | Modify the nwcfg bit definitions to have 32-bit by removing the extra nibble. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | nand: arasan_nfc: Clear ecc on bit while sending read commandSiva Durga Prasad Paladugu2016-11-15-0/+2
| | | | | | | | | | | | | | | | | | | | Clear ecc ON bit while sending read command as all types of read command(like reading spare) doesnt need ECC to be enabled. It has been anyway taken care in other places whereever required using arasan_nand_enable_ecc(). Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynq: nand: Runtime detection of nand buswidth through slcrMichal Simek2016-11-15-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to check the buswidth on nand flash at runtime based on nand MIO configurations done by FSBL. User needs to correctly configure the MIO's based on the buswidth supported by the nand flash which is present on the board. Added nand8 and nand16 @periph names on slcr driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynq: nand: Enable Nand flash controller driver a zynq boardSiva Durga Prasad Paladugu2016-11-15-0/+9
| | | | | | | | | | | | | | | | Enable zynq Nand flash controller driver for a zynq ZC770 XM011(dc2) board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | mtd: nand: zynq_nand: Add nand driver support for zynqSiva Durga Prasad Paladugu2016-11-15-0/+1194
| | | | | | | | | | | | | | Add nand flash controller driver support for zynq SoC. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Add support for the topic-miami system-on-modules and carrier boardsMike Looijmans2016-11-15-0/+1115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The topic-miami SoMs contain a Zynq xc7z015 or xc7z030 SoC, 1GB DDR3L RAM, 32MB QSPI NOR flash and 256MB NAND flash. The topic-miamiplus SoMs contain a Zynq xc7z035, xc7z045 or xc7z100 SoC, 2x 1GB DDR3L RAM, 64MB dual-parallel QSPI flash, clock sources and a fan controller. The "Florida" carrier boards add SD, USB, ethernet and other interfaces. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Make SYS_VENDOR configurableMike Looijmans2016-11-15-0/+1
| | | | | | | | | | | | | | | | Add a string description for SYS_VENDOR to allow configuring boards from other vendors than just "xilinx". Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | tools: mkimage: Check if file is regular fileMichal Simek2016-11-15-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | Current Makefile.spl passes -R parameter which is not empty and pointing to ./ folder. "./tools/mkimage -T zynqmpimage -R ./"" -d spl/u-boot-spl.bin spl/boot.bin" That's why mkimage is trying to parse ./ file and generate register init which is wrong. Check that passed filename is regular file. If not do not work with it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | tools: mkimage: Add support for initialization table for Zynq and ZynqMPMike Looijmans2016-11-15-2/+72
|/ | | | | | | | | | | | | | | | | | The Zynq/ZynqMP boot.bin file contains a region for register initialization data. Filling in proper values in this table can reduce boot time (e.g. about 50ms faster on QSPI boot) and also reduce the size of the SPL binary. The table is a simple text file with register+data on each line. Other lines are simply skipped. The file can be passed to mkimage using the "-R" parameter. It is recommended to add reg init file to board folder. For example: CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/xilinx_zynqmp_zcu102/reg.int Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Prepare v2016.11Tom Rini2016-11-14-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* MAINTAINERS: mark sunxi status as OrphanHans de Goede2016-11-14-3/+1
| | | | | | | | | | | | Ian has not had any time for sunxi for some time now and I'm in the same situation now, so I'm stepping down as sunxi custodian and marking the sunxi support as Orphan. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* video: bmp: Fix compilation errors with CONFIG_BMP_xxBPP enabledStefan Roese2016-11-13-3/+3
| | | | | | | | | | | | | | | | | | | | | Compiling the 'bmp' command with DM and having one of the following macros enabled: CONFIG_BMP_16BPP, CONFIG_BMP_24BPP ONFIG_BMP_32BPP generates this error: drivers/video/video_bmp.c: In function ‘video_bmp_display’: drivers/video/video_bmp.c:315:22: error: ‘lcd_line_length’ undeclared (first use in this function) fb -= width * 2 + lcd_line_length; ^ This patch moves to using the correct variable instead and enables the 'bmp' command for DM again. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Anatolij Gustschin <agust@denx.de>
* net: write enetaddr down to hardware on env_callbackMarek Vasut2016-11-13-0/+1
| | | | | | | | | | | | If mac-address is changed using "setenv ethaddr ...." command the new mac-adress also must be written into the responsible ethernet driver. This fixes the legacy ethernet handling. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
* spi: ti_qspi: Fix baudrate divider calculationVignesh R2016-11-13-9/+7
| | | | | | | | | Fix the divider calculation logic to choose a value so that the resulting baudrate is either equal to or closest possible baudrate less than the requested value. While at that, cleanup ti_spi_set_speed(). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* ARM: dts: dra7xx: Update spi-max-frequency for qspi slave nodeVignesh R2016-11-13-2/+2
| | | | | | | | | Update the spi-max-frequency property of m25p80 flash slave to match that of TI QSPI controller node, so that QSPI operations happen at maximum supported frequency of 76.8MHz. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: k2g: Update PLL Multiplier and divider valuesLokesh Vutla2016-11-13-1/+1
| | | | | | | | | | | Only a certain set of PLLM/D values are recommended to configure the DDR at the required speeds for a given clock input frequency. Updating these values as specified in Data Sheet[1] Table 5-18 [1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: PLL: Enable glitch free initialization sequenceLokesh Vutla2016-11-13-8/+8
| | | | | | | | | | Update the PLL initialization sequence to avoid glitches while programming. User guide for the same is available at[1]. [1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: Set TTB XN bit in case DCACHE_OFF for LPAE modeKeerthy2016-11-13-1/+6
| | | | | | | | | | | | | | | | | While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: print the cache config option in hex instead of decimalKeerthy2016-11-13-1/+1
| | | | | | | Printing the option value in hex makes it more comprehensible. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* mx6ull_14x14_evk: Add README fileDiego Dorta2016-11-13-0/+36
| | | | | | | | | Add a README file to help users getting started with the board. Signed-off-by: Diego Dorta <diego.dorta@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
generated by cgit v1.1 at 2024-11-07 19:04:46 +0000