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| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2016-09-29 11:44:41 -0700 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2016-11-15 15:28:05 +0100 |
| commit | 0cba6abbba5c0bd5c80e652c35d0bd74e644a49e (patch) | |
| tree | e8f1197d4d81af1511dd360fa04bf5aa1ec8fac2 | |
| parent | 05c59d0bc83f28888e5f2cc11b679a721605a46b (diff) | |
| download | u-boot-imx-0cba6abbba5c0bd5c80e652c35d0bd74e644a49e.zip u-boot-imx-0cba6abbba5c0bd5c80e652c35d0bd74e644a49e.tar.gz u-boot-imx-0cba6abbba5c0bd5c80e652c35d0bd74e644a49e.tar.bz2 | |
ARM64: zynqmp: Adjust to new SMC interface to get silicon version
The new FW interface returns the IDCODE and version register, leaving
extracting bitfields to the caller.
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| -rw-r--r-- | board/xilinx/zynqmp/zynqmp.c | 11 | ||||
| -rw-r--r-- | include/zynqmppl.h | 6 |
2 files changed, 17 insertions, 0 deletions
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index ba4dfbb..b0acaa5 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -86,6 +86,17 @@ static int chip_id(void) smc_call(®s); + /* + * SMC returns: + * regs[0][31:0] = status of the operation + * regs[0][63:32] = CSU.IDCODE register + * regs[1][31:0] = CSU.version register + */ + regs.regs[0] = upper_32_bits(regs.regs[0]); + regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | + ZYNQMP_CSU_IDCODE_SVD_MASK; + regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; + return regs.regs[0]; } diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 542ace9..fb5200e 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -16,6 +16,12 @@ #define ZYNQMP_FPGA_OP_LOAD (1 << 1) #define ZYNQMP_FPGA_OP_DONE (1 << 2) +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ + ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) +#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 +#define ZYNQMP_CSU_IDCODE_SVD_MASK (0xe << ZYNQMP_CSU_IDCODE_SVD_SHIFT) + extern struct xilinx_fpga_op zynqmp_op; #define XILINX_ZYNQMP_DESC \ |