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* armv8: caches: Added routine to set non cacheable regionSiva Durga Prasad Paladugu2015-07-31-10/+55
| | | | | | | | | | | Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-07-29-103/+4639
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| * T210: Add support for 64-bit T210-based P2571 boardTom Warren2015-07-28-0/+617
| | | | | | | | | | | | | | | | | | | | | | Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). Signed-off-by: Tom Warren <twarren@nvidia.com>
| * P2571: dts: Add DT file for Tegra210 P2571 boardTom Warren2015-07-28-1/+108
| | | | | | | | | | | | Based on T124 Venice2. SDMMC1 is SD-card slot. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: Tegra210: Add support to common Tegra source/config filesTom Warren2015-07-28-43/+509
| | | | | | | | | | | | | | | | | | | | | | Derived from Tegra124, modified as appropriate during T210 board bringup. Cleaned up debug statements to conserve string space, too. This also adds misc 64-bit changes from Thierry Reding/Stephen Warren. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: Tegra210: Add SoC code/include files for T210Tom Warren2015-07-28-0/+3275
| | | | | | | | | | | | | | | | | | | | | | All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra: Rework KConfig options to allow 64-bit builds (T210)Tom Warren2015-07-28-11/+18
| | | | | | | | | | | | | | | | | | | | Moved Tegra config options to mach-tegra/Kconfig so that both 32-bit and 64-bit builds can co-exist for Tegra SoCs. T210 will be 64-bit only (no SPL) and will require a 32-bit AVP/BPMP loader. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra210: Fix 64-bit build warning about save_boot_params_ret()Tom Warren2015-07-28-0/+2
| | | | | | | | | | | | | | | | Simon's 'tegra124: Implement spl_was_boot_source()' needs a prototype for save_boot_params_ret() to build cleanly for 64-bit Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Use architected timer on ARMv8Thierry Reding2015-07-28-0/+3
| | | | | | | | | | | | | | | | ARMv8 requires an architected timer to be present, so it can be used instead of the Tegra US timer. This allows for better code reuse. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Initialize timer earlierThierry Reding2015-07-28-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | A subsequent patch will enable the use of the architected timer on ARMv8. Doing so implies that udelay() will be backed by this timer implementation, and hence the architected timer must be ready when udelay() is first called. The first time udelay() is used is while resetting the debug UART, which happens very early. Make sure that arch_timer_init() is called before that. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: Disable SPL and non-cached memory on 64-bitThierry Reding2015-07-28-0/+4
| | | | | | | | | | | | | | | | | | | | For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in AArch64 mode so that we don't need the SPL. Non-cached memory is not implemented (yet) for 64-bit ARM. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Use standard cache enable for 64-bitThierry Reding2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | On 64-bit SoCs the I-cache isn't enabled in early code, so the default cache enable functions for 64-bit ARM can be used. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCsThierry Reding2015-07-28-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most peripherals on Tegra can do DMA only to the lower 32-bit address space, even on 64-bit SoCs. This limitation is typically overcome by the use of an IOMMU. Since the IOMMU is not entirely trivial to set up and serves no other purpose (I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to the lower 32-bit address space for RAM. This ensures that the physical addresses of buffers that are programmed into the various DMA engines are valid and don't alias to lower addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * fdt: Fix fdtdec_get_addr_size() for 64-bitThierry Reding2015-07-28-20/+36
| | | | | | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * armv8/cache: Fix page table creationThierry Reding2015-07-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While generating the page tables, a running integer index is shifted by SECTION_SHIFT (29) and causes overflow for any integer bigger than 7. The page tables therefore alias to the same 8 sections and cause U-Boot to hang once the MMU is enabled. Fix this by making the index a 64-bit unsigned integer and so avoid the overflow. swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and "j" varies depending on RAM size; from 4 to 11 for a board with 4GB at physical address 2GB, as some Tegra boards have. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN valuesThierry Reding2015-07-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN can only accept certain values, and the set of acceptable values differs between the AArch32 and AArch64 instructions sets. The default value of CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0 assembly so it can handle completely arbitrary values. Signed-off-by: Thierry Reding <treding@nvidia.com> [twarren: trimmed Thierry's patch to remove changes already present] Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, cleaned up patch, wrote description, re-wrote subject] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * ARM: tegra: Build warning fixes for 64-bitThierry Reding2015-07-27-3/+3
| | | | | | | | | | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, stripped out changes not strictly related to warnings] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * mmc: tegra: Build warning fixes for 64-bitThierry Reding2015-07-27-3/+3
| | | | | | | | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * i2c: tegra: Build warning fixes for 64-bitThierry Reding2015-07-27-2/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * dfu: fix 64-bit compile warningsStephen Warren2015-07-27-3/+3
| | | | | | | | | | | | | | | | | | | | | | Use %p to print pointers. The max value of (i_buf - i_buf_start) should be dfu_buf_size, which is an unsigned long, so cast the pointer difference to that type to print. Change-Id: Iee242df9f8eb091aecfe0cea4c282b28b547acfe Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pxe: add AArch64 image supportStephen Warren2015-07-27-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sysboot and pxe commands currently support either U-Boot formats or raw zImages. Add support for the AArch64 Linux port's native image format too. As with zImage support, there is no auto-detection of the native image format. Rather, if the image is auto-detected as a U-Boot format, U-Boot will try to interpret it as such. Otherwise, U-Boot will fall back to a raw/native image format, if one is enabled. My belief is that CONFIG_CMD_BOOTZ won't ever be enabled for any AArch64 port, hence there's never a need to differentiate between CONFIG_CMD_ _BOOTI and _BOOTZ at run-time; compile-time will do. Even if this isn't true, we want to prefer _BOOTI over _BOOTZ when defined, since _BOOTI is definitely the native format for AArch64. Change-Id: I83c5cc7566032afd72516de46f4e5eb7a780284a Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra124: Expand SPL space by 8KBSimon Glass2015-07-27-1/+1
| | | | | | | | | | | | | | | | We are getting very close to running out of space in SPL, and with the currently Chrome OS gcc 4.9 we exceed the limit. Add a litle more space. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: nyan-big: Allow TPM on I2CSimon Glass2015-07-27-4/+4
| | | | | | | | | | | | | | | | | | | | | | Enable the I2C3 pins so that the TPM can be used. Note: There is an DP change also, caused by running board-to-uboot.py script in the latest tegra-pinmux-script tree. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra124: Implement spl_was_boot_source()Simon Glass2015-07-27-0/+16
| | | | | | | | | | | | | | Add an implementation of this function for Tegra. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | patman: add distutils based installerChris Packham2015-07-28-8/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To make it easier to use patman on other projects add a distutils style installer. Now patman can be installed with cd u-boot/tools/patman && python setup.py install There are also the usual distutils options for creating source/binary distributions of patman. Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Reserve PCIe ECAM address range in the E820 tableBin Meng2015-07-28-1/+20
| | | | | | | | | | | | | | | | We should mark PCIe ECAM address range in the E820 table as reserved otherwise kernel will not attempt to use ECAM. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Turn on PCIe ECAM address range decoding on Q35Bin Meng2015-07-28-0/+8
| | | | | | | | | | | | | | Turn on PCIe ECAM address range decoding on Q35. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Enable writing MP tableBin Meng2015-07-28-3/+58
| | | | | | | | | | | | | | Enable writing MP table for QEMU boads (i440fx and q35). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Allow cpu-x86 driver to be probed for UPBin Meng2015-07-28-0/+9
| | | | | | | | | | | | | | | | Currently cpu-x86 driver is probed only for SMP. We add the same support for UP when there is only one cpu node in the deive tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Enable I/O APIC chip select on PIIX3Bin Meng2015-07-28-2/+11
| | | | | | | | | | | | | | | | The PIIX3 chipset does not integrate an I/O APIC, instead it supports connecting to an external I/O APIC which needs to be enabled manually. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: mpspec: Move writing ISA interrupt entry after PCIBin Meng2015-07-28-5/+21
| | | | | | | | | | | | | | | | | | | | On some platforms the I/O APIC interrupt pin#0-15 may be connected to platform pci devices' interrupt pin. In such cases the legacy ISA IRQ is not available so we should not write ISA interrupt entry if it is already occupied. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APICBin Meng2015-07-28-7/+34
| | | | | | | | | | | | | | | | | | Currently during writing MP table I/O interrupt assignment entry, we assume the PIRQ is directly mapped to I/O APIC INTPIN#16-23, which however is not always the case on some platforms. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Convert to use driver model pci on queensbay/crownbayBin Meng2015-07-28-53/+6
| | | | | | | | | | | | Move to driver model pci for Intel queensbay/crownbay. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: pci: Support bridge device configuration correctlyBin Meng2015-07-28-18/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: pci: Pass only device/function to pci_bus_find_devfn()Bin Meng2015-07-28-1/+1
| | | | | | | | | | | | | | | | In dm_pci_hose_probe_bus(), pci_bus_find_devfn() is called with a bdf which includes a bus number, but it really should not as this routine only expects a device/function encoding. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: pci: Use complete bdf in all pci config read/write routinesBin Meng2015-07-28-27/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently pci_bus_read_config() and pci_bus_write_config() are called with bus number masked off in the parameter bdf, and bus number is supposed to be added back in the bridge driver's pci config read/write ops if the device is behind a pci bridge. However this logic only works for a pci topology where there is only one bridge off the root controller. If there is addtional bridge in the system, the logic will create a non-existent bdf where its bus number gets accumulated across bridges. To correct this, we change all pci config read/write routines to use complete bdf all the way up to the root controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: pci: Correct primary/secondary/subordinate bus number assignmentBin Meng2015-07-28-0/+9
| | | | | | | | | | | | | | | | | | In driver model, each pci bridge device has its own hose structure. hose->first_busno points to the bridge device's device number, so we should not substract hose->first_busno before programming the bridge device's primary/secondary/subordinate bus number registers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | Fix incorrect comments in linker_lists.hBin Meng2015-07-28-10/+10
| | | | | | | | | | | | | | This corrects several typos in the comment block as well as some indentions and nits in the linker_lists.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | buildman: Correct '--fetch-arch' command documentationBin Meng2015-07-28-2/+2
| | | | | | | | | | | | | | The doc wrongly put sandbox in the '--fetch-arch' command. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: pci: Do not assign irq 0 to pci deviceBin Meng2015-07-28-0/+2
| | | | | | | | | | | | | | IRQ 0 is reserved and should not be assigned to pci device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: pci: Assign pci irqs to all functionsBin Meng2015-07-28-14/+19
| | | | | | | | | | | | | | | | We need walk through all functions within a PCI device and assign their IRQs accordingly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Enable DM RTC support for all x86 boardsBin Meng2015-07-28-9/+36
| | | | | | | | | | | | | | | | Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> (Squashed in 'x86: Fix RTC build error on ivybridge')
* | x86: Change pci option rom area MTRR setting to cacheableBin Meng2015-07-28-7/+22
| | | | | | | | | | | | | | Turn on cache on the pci option rom area to improve the performance. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Simplify architecture defined exception handling in irq_llsr()Bin Meng2015-07-28-105/+46
| | | | | | | | | | | | | | | | | | | | | | | | Instead of using switch..case for architecture defined exceptions, simply unify the handling by printing a message of exception name, followed by registers dump then halt the CPU. With this unification, it also fixes the wrong exception numbers for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 15/16/17/18. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Display correct CS/EIP/EFLAGS when there is an error codeBin Meng2015-07-28-4/+65
| | | | | | | | | | | | | | | | | | Some exceptions cause an error code to be saved on the current stack after the EIP value. We should extract CS/EIP/EFLAGS from different position on the stack based on the exception number. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-07-28-117/+1427
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| * | cmd_mp: Add support for showing all CPU status by one commandMichal Simek2015-07-28-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | Use one command for showing overall CPU status than several without knowing how many cpus is available in the system. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | spi: zynq_spi: Simplify debug macroMichal Simek2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | Trivial fix. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: Fix typo in Makefile about custom ps7_init fileMichal Simek2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | Trivial fix. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | net: gem: Extend timeout valueMichal Simek2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | Extend time for MDIO. (Because of zed board) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.1 at 2024-10-09 01:21:45 +0000