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* Merge branch 'u-boot/master' into u-boot-arm/masterAlbert ARIBAUD2013-07-25-94824/+11753
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| * Merge branch 'master' of git://git.denx.de/u-boot-nds32Tom Rini2013-07-25-43/+384
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| | * nds32: Enable FPU if the version of CPU supportedken kuo2013-07-25-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some version of Andes core support FPU coprocessor, if this is the case, and toolchain support FPU instruction set, we should enable it at low level initialization time. Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| | * nds32: Update <asm/io.h> and <asm/setup.h> with SPDX license identifiersTom Rini2013-07-25-6/+2
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| | * nds32: Convert Makefiles to use COBJS-y styleken kuo2013-07-25-21/+24
| | | | | | | | | | | | | | | Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| | * nds32: ag101/ag102: Fix setting lastdec and now valuesAxel Lin2013-07-24-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer3 counter unit for lastdesc and now values are inconsistent in current code. The unit of "readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2)" is second. However, CONFIG_SYS_HZ is defined as 1000 in board config file. This means the accuracy of "lastdec" and "now" should be in millisecond, thus fix the equation to set lastdec and now variables accordingly. Signed-off-by: Axel Lin <axel.lin@ingics.com>
| | * nds32: Enable the function of passing parameters to Linuxken kuo2013-07-24-0/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a header file, setup.h, which copy from Linux source code, this file contain structures are used to pass initialisation parameters to Linux. Enable this function on adp-ag101/adp-ag101p target Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| | * nds32: Enable SDIO and EXT2 command support for Andes boardken kuo2013-07-24-0/+4
| | | | | | | | | | | | | | | Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| | * nds32: Enable two banks of SDRAM on Andes boardken kuo2013-07-24-5/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | The original adp-ag101/adp-ag101p initialize only one bank(64MB) by default at boot time, but it is not enough for some application, so increasing to two banks(128M). Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com> Cc: Macpaul Lin <macpaul@gmail.com>
| | * nds32: adp-ag102: use 'faraday/ftpci100.h' for pci_ftpci_initGabor Juhos2013-07-24-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to improper external function declaration, building U-Boot for the adp-ag102 board shows this warning: adp-ag102.c: In function 'pci_init_board': adp-ag102.c:95: warning: function declaration isn't a prototype Include the 'faraday/ftpci100.h' header which provides the proper declaration and remove the local declaration to get rid of the warning. Compile tested only. Cc: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
| | * pci: move pci_ftpci100.h to include/faraday/ftpci100.hGabor Juhos2013-07-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though the header files is used only by the pci_ftpci100 driver, it contains declaration for a function which is used by external code. Move the header file to a common location which lets external code use it. Compile tested only. Cc: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
| | * pci: add prototype for pci_ftpci_init() functionGabor Juhos2013-07-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_ftpci_init() function is implemented in 'drivers/pci/pci_ftpci100.c' however it is always called by external code. Add function declaration into ftpci100.h to make it visible for external code. Compile tested only. Cc: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
| | * block: constify sect_buf argument of ide_write_dataGabor Juhos2013-07-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a const keyword to the sect_buf argument of ide_write_data to fix the following warning: cmd_ide.c: In function '__ide_output_data': cmd_ide.c:548: warning: passing argument 2 of 'ide_write_data' discards qualifiers from pointer target type /devel/u-boot.git/include/ide.h:76: note: expected 'ulong *' but argument is of type 'const ulong *' Also modify the driver-model documentation to match with the new prototype. Compile tested only. Cc: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
| | * mmc: ftsdc010_mci: fix build error if CONFIG_FTSDC010_SDIO is not definedGabor Juhos2013-07-24-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FTSDC010_DCR_FIFO_RST symbol is conditionally defined in <faraday/ftsdc010.h> and it is available available when CONFIG_FTSDC010_SDIO is enabled. However the actual driver code unconditionally uses the FTSDC010_DCR_FIFO_RST constant and this causes build error if CONFIG_FTSDC010_SDIO is not enabled. The following error happens when compiling for the adp-ag101 board: ftsdc010_mci.c: In function 'ftsdc010_request': ftsdc010_mci.c:178: error: 'FTSDC010_DCR_FIFO_RST' undeclared (first use in this function) ftsdc010_mci.c:178: error: (Each undeclared identifier is reported only once ftsdc010_mci.c:178: error: for each function it appears in.) The patch ensures that the FTSDC010_DCR_FIFO_RST symbol gets used only if CONFIG_FTSDC010_SDIO is defined. Compile tested only. Cc: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Reviewed-by: Kuo-Jung Su <dantesu@faraday-tech.com>
| | * nds32: introduce macros for bit manipulationGabor Juhos2013-07-24-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot does not compile for the adp-ag101 boards since commit f6c3b34697bf8bf05cb4e81c2fd3cadb9a98daea (mmc: update Faraday FTSDC010 for rw performance) The driver assumes that the bit manipulation macros are provided by all architectures. This is not the case for nds32 and it causes a build error like this: ftsdc010_mci.c: In function 'ftsdc010_clkset': ftsdc010_mci.c:118: warning: implicit declaration of function 'setbits_le32' ftsdc010_mci.c:123: warning: implicit declaration of function 'clrbits_le32' drivers/mmc/libmmc.o: In function `ftsdc010_request': /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:234: undefined reference to `setbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:243: undefined reference to `clrbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:234: undefined reference to `clrbits_le32' drivers/mmc/libmmc.o: In function `ftsdc010_clkset': /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:118: undefined reference to `clrbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:118: undefined reference to `clrbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:121: undefined reference to `setbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:123: undefined reference to `setbits_le32' /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:123: undefined reference to `setbits_le32' The patch adds bit manipulation macros for the nds32 architecture to avoid the errors. The macros are copied from the ARM implementation. Compile tested only. Cc: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
| * | qemu-malta: Update for SPDX license identifiersTom Rini2013-07-25-44/+7
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-07-25-50/+1108
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflict over SPDX changes means that one change was effectively dropped as it was fixing typos in a removed hunk of text. Conflicts: arch/mips/cpu/mips64/start.S Signed-off-by: Tom Rini <trini@ti.com>
| | * | MIPS: mips32/cache.S: use v1 register for indirect function callsGabor Juhos2013-07-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: mips32/cache.S: store cache line size in t8 registerGabor Juhos2013-07-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: mips32/cache.S: save return address in t9 registerGabor Juhos2013-07-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: xburst/start.S: rework relocation info checkGabor Juhos2013-07-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make it similar to the code in mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: xburst/start.S: use t8 register for dynamic relocationGabor Juhos2013-07-24-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: xburst/start.S: save gd in s0 registerGabor Juhos2013-07-24-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: xburst/start.S: save relocation offset in s1 registerGabor Juhos2013-07-24-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: xburst/start.S: save relocation address in s2 registerGabor Juhos2013-07-24-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips{32,64}/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: mips32/start.S: rework relocation info checkGabor Juhos2013-07-24-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make it similar to the code in mips64/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: mips32/start.S: use t8 register for dynamic relocationGabor Juhos2013-07-24-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synchronize the code with mips64/start.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: mips32/cache.S: remove superfluous register assignmentGabor Juhos2013-07-24-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The t4 register already holds the cache line size, and the value of the register is not changed in mips_init_icache. Get the cache line size value from t4 for mips_init_dcache as well and remove the superfluous assignment of t5 register. Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
| | * | MIPS: remove obsolete TODO itemsGabor Juhos2013-07-24-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS code uses centralized u-boot.lds script already, and dynamic relocation is supported as well. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: mips64/interrupt.c: remove superfluous includeGabor Juhos2013-07-24-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Nothing is used from asm/mipsregs.h. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: mips32/time.c: fix checkpatch errors/warningsGabor Juhos2013-07-24-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Checking mips32/time.c with checkpatch.pl shows this: arch/mips/cpu/mips32/time.c:30: WARNING: line over 80 characters arch/mips/cpu/mips32/time.c:57: ERROR: return is not a function, parentheses are not required total: 1 errors, 1 warnings, 0 checks, 85 lines checked Fix the code to make checkpatch.pl happy. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: qemu-malta: bring up ethernetGabor Juhos2013-07-24-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qemu emulates a PCNET PCI card for the Malta CoreLV board. Enable the pcnet driver and add board specific ethernet initialization function to bring it up. Also enable the CONFIG_CMD_NET and CONFIG_CMD_PING options. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: qemu-malta: add PCI supportGabor Juhos2013-07-24-0/+216
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qemu emulates the Galileo GT64120 System Controller which provides a CPU bus to PCI bus bridge. The patch adds driver for this bridge and enables PCI support for the emulated Malta board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: qemu-malta: setup GT64120 registers as done by YAMONGabor Juhos2013-07-24-1/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the GT64120 register base to 0x1be00000 and setup PCI BAR registers as done by the original YAMON bootloader. This is needed for running Linux kernel. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: qemu-malta: enable flash supportGabor Juhos2013-07-24-2/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: qemu-malta: add reset supportGabor Juhos2013-07-24-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS Malta board has a SOFTRES register. Writing a magic value into that register initiates a board reset. Use this feature to implement reset support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: qemu-malta: add support for emulated MIPS Malta boardGabor Juhos2013-07-24-0/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add minimal support for the MIPS Malta CoreLV board emulated by Qemu. The only supported peripherial is the UART. This is enough to boot U-Boot to the command prompt both in little and big endian mode. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: start.S: emulate REVISION register for qemu-maltaGabor Juhos2013-07-24-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the origial Malta boards the REVISION register is accessible at the 0x1fc00010 address. The contents of this register gives information about the revision of the Malta and Core Boards. This register is used by the Linux kernel to identify the actual board it is running on. However the register is not emulated properly by Qemu, so put a hardcoded value into the flash to make Linux work. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: import gt64120.h header from LinuxGabor Juhos2013-07-24-0/+550
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux specific register access macros, the extern function declarations and the UL suffixes has been removed. The header file will be used for the qemu-malta board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | net: pcnet: use pci_virt_to_mem to obtain buffer addressesGabor Juhos2013-07-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pcnet driver uses the pci_phys_to_mem function to get the memory address of the DMA buffers. This This assumes an 1:1 mapping between the PCI and physical memory which is not true on all platforms. On MIPS platform U-Boot is running within a mapped memory region, and the pci_phys_to_mem macro can't be used to obtain the memory address of the buffers. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
| | * | MIPS: mips64: fix typos in copyright text of start.STom Rini2013-07-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Conflicts: arch/mips/cpu/mips64/start.S Signed-off-by: Tom Rini <trini@ti.com>
| * | | drivers/i2c: Update fti2c010.[ch], i2c_core.c to use SPDX identifiersTom Rini2013-07-25-17/+3
| | | | | | | | | | | | | | | | | | | | Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-07-24-2620/+3124
| |\ \ \ | | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sandburst-specific i2c drivers have been deleted, conflict was just over the SPDX conversion. Conflicts: board/sandburst/common/ppc440gx_i2c.c board/sandburst/common/ppc440gx_i2c.h Signed-off-by: Tom Rini <trini@ti.com>
| | * | fdtdec: Add compatible string for High speed i2cnaveen krishna chatradhi2013-07-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a new COMPAT string exynos5-hsi2c for high speed i2c controller available on exynos5 SoCs from Samsung. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
| | * | i2c: add Faraday FTI2C010 I2C controller supportKuo-Jung Su2013-07-23-0/+451
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Faraday FTI2C010 is a multi-function I2C controller which supports both master and slave mode. This patch simplily implements the master mode only. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Heiko Schocher <hs@denx.de>
| | * | I2C: mxc_i2c: Add support for Vybrid VF610 platformAlison Wang2013-07-23-7/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Vybrid VF610 platform. There are some differences between i.MX6 and Vybrid for I2C controller. (1) The registers' offset are different. (2) The I2C clock divider values are different. (3) In I2C control register, the enable/disable/reset bit is inverted for Vybrid comparing to i.MX6. (4) In I2C status register, the interrupt flag bit is cleared by writing "1" for Vybrid. For i.MX6, this bit is cleared by writing "0". (5) In I2C status register, the arbitration lost flag bit is cleared by writing "1" for Vybrid. For i.MX6, this bit is cleared by writing "0". Signed-off-by: Alison Wang <b18965@freescale.com>
| | * | vf610: Add I2C support for Vybrid VF610 platformAlison Wang2013-07-23-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds I2C support for Vybrid VF610 platform and adds I2C0 support to VF610TWR board. Signed-off-by: Alison Wang <b18965@freescale.com>
| | * | cmd_i2c: Use ARRAY_SIZE instead of reinventing itAxel Lin2013-07-23-4/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * | arm/km: fix u-boot update functionalityHolger Brunck2013-07-23-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the new I2C framework we need to adapt the u-boot update function. Due to the new framework all i2c leafs behind a mux are present in the system and not only those who are defined and used. So it is bus number 5 after the rework. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Heiko Schocher <hs@denx.de> cc: Prafulla Wadaskar <prafulla@marvell.com>
| | * | i2c, ppc4xx_i2c: switch to new multibus/multiadapter supportDirk Eibach2013-07-23-1025/+465
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-01 02:37:19 +0000