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| * | efi: Add support for a hello world test programSimon Glass2016-11-14-6/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to have a basic sanity check for EFI loader support. Add a 'bootefi hello' command which loads HelloWord.efi and runs it under U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> [agraf: Fix documentation, add unfulfilled kconfig dep] Signed-off-by: Alexander Graf <agraf@suse.de>
| * | efi: Makefile: Export variables for use with EFISimon Glass2016-11-14-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building an EFI app we need three things: - start-up code - relocation code - link script These are all different for each architecture. We also need special compiler flags in some cases. Add top-level Makefile variables for these along with documentation. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | x86: Tidy up selection of building the EFI stubSimon Glass2016-11-14-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we use a CONFIG option in efi.h to determine whether we are building the EFI stub or not. This means that the same header cannot be used for EFI_LOADER support. The CONFIG option will be enabled for the whole build, even when not building the stub. Use a different define instead, set up just for the files that make up the stub. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | efi: Fix debug message address formatSimon Glass2016-11-14-1/+1
| | | | | | | | | | | | | | | | | | | | | This should use U-Boot's standard format for hex address. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | efi: Correct cache flush alignmentSimon Glass2016-11-14-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Make sure that the cache flushes correctly by ensuring that the end address is correctly aligned. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | x86: Correct a build warning in x86 tablesSimon Glass2016-11-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is a build warning for three x86 boards since write_smbios_table_wrapper() is not used. Fix it. Fixes: e824cf3f (smbios: Allow compilation on 64bit systems) Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | efi_loader: console: Correctly report modesEmmanuel Vadot2016-11-14-16/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for EFI console modes. Mode 0 is always 80x25 and present by EFI specification. Mode 1 is always 80x50 and not mandatory. Mode 2 and above is freely usable. If the terminal can handle mode 1, we mark it as supported. If the terminal size is greater than mode 0 and different than mode 1, we install it as mode 2. Modes can be switch with cout_set_mode. Changes in V5: Correctly detect mode before enabling mode 2. Changes in V4: Reset cursor positon on mode switch Use local variables in console query code Changes in V3: Valid mode are 0 to EFIMode-1 Fix style Changes in V2: Add mode switch Report only the modes that we support Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | efi: Use device device path type Messaging for network interface nodeOleksandr Tymoshenko2016-11-14-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | When adding network interface node use Messaging device path with subtype MAC Address and device's MAC address as a value instead of Media Device path type with subtype File Path and path "Net" Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | efi_loader: fix depends on line of EFI_LOADERMasahiro Yamada2016-11-14-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | This line is shown as depends on (ARM64 ||\302\240ARM) && OF_LIBFDT on my Emacs. Use ASCII characters only. Assuming it is (ARM64 || ARM), remove the redundancy. Unlike Linux, CONFIG_ARM includes CONFIG_ARM64 in U-Boot. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* | ARM64: zynqmp: Adding prefetchable memory space to pcieBharat Kumar Gogada2016-11-15-2/+3
| | | | | | | | | | | | | | | | | | | | Adding prefetchable memory space to pcie device tree node. Shifting configuration space to 64-bit address space. Removing pcie device tree node from amba as it requires size-cells=<2> in order to access 64-bit address space. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add clocks for LPDDMAKedareswara rao Appana2016-11-15-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zynqmp DMA driver expects two clocks (main clock and apb clock) For LPDDMA channels the two clocks are missing in the Dma node resulting probe failure. xilinx-zynqmp-dma ffa80000.dma: main clock not found. xilinx-zynqmp-dma ffa80000.dma: Probing channel failed xilinx-zynqmp-dma: probe of ffa80000.dma failed with error -2 This patch fixes this issue. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add description for LPDDMA channel usageKedareswara rao Appana2016-11-15-1/+4
| | | | | | | | | | | | | | | | | | | | | | LPDDMA default allows only secured access. inorder to enable these dma channels, one should ensure that it allows non secure access. This patch updates the same. Reported-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Use 64bit size cell format for main amba busMichal Simek2016-11-15-65/+65
| | | | | | | | | | | | | | Use 64bit size cell for main amba bus instead of 32bit because PCIe node requires it Change 64bit sizes also for all others IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add ocm node in dtsiNaga Sureshkumar Relli2016-11-15-0/+7
| | | | | | | | | | | | | | | | This patch adds ocm controller node in zynqmp.dtsi. needed for OCM edac support. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add device tree properties for ZynqMP GT coreAnurag Kumar Vulisha2016-11-15-0/+23
| | | | | | | | | | | | | | | | | | This patch adds the ZynqMP GT core device-tree properties for zynqmp.dtsi file. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Revert "ARM64: zynqmp: Added broken-tuning property to SD, eMMC nodes"Michal Simek2016-11-15-2/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit bd750e7a6c515c081b72d4ef108a2bfa691a3fd1 Implemented the new workaround for auto tuning based on zynqmp compatible string, so removed the 'broken-tuning' property. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: change sdhci compatible string.Sai Krishna Potthuri2016-11-15-2/+9
| | | | | | | | | | | | | | | | This patch changes the compatible string for sdhci node, adds "xlnx,device_id" and "xlnx,mio_bank" property to sdhci node. Signed-off-by: Sai Krishna Potthuri <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: List all SMMU idsMichal Simek2016-11-15-1/+72
| | | | | | | | | | | | Add SMMU description for all tested IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add support for zynqmp fpga managerNava kishore Manne2016-11-15-0/+4
| | | | | | | | | | | | | | Add support for zynqmp fpga manager. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add cortexa53 edac nodeNaga Sureshkumar Relli2016-11-15-0/+4
| | | | | | | | | | | | | | | | This patch adds edac node for arm cortexa53 to report errors on L1 and L2 caches. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Revert "ARM64: zynqmp: Add serdes address space dp driver"Michal Simek2016-11-15-2/+1
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 786db82bd5bf09cc8f78c8b14445e843d7566b1c. Since we are using serdes driver , no need of mapping serdes register space into DP driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: drm: Add DMA indexHyun Kwon2016-11-15-3/+5
| | | | | | | | | | | | | | | | Each plane can be associated with multiple DMA channels. So add index for each DMA channel. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Sync gpio node propertiesMichal Simek2016-11-15-2/+2
| | | | | | | | | | | | Keep dtsi in sync with mainline kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove xlnx,id propertyMichal Simek2016-11-15-16/+0
| | | | | | | | | | | | | | Remove unused xlnx,id property because it is not the part of DT binding. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: pci: Updating device tree as per upstreamBharat Kumar Gogada2016-11-15-1/+4
| | | | | | | | | | | | | | | | Updating required device tree changes as per mainlined driver from 4.6 kernel. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Support for multiple PM IDs assigned to a PM domainFilip Drazic2016-11-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, it was assumed that there is a 1:1 mapping between PM ID defined in the platform firmware and a PM domain. However, there can be a situation where multiple PM IDs belong to a single PM domain (e.g. PM IDs for GPU and two pixel processors correspond to a single PM domain). This patch adds support for assigning more than one PM ID to a single PM domain. Updated documentation accordingly. Assigned pixel processors PM IDs to GPU PM domain. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Add PM domains for GPU and PCIEFilip Drazic2016-11-15-0/+12
| | | | | | | | | | | | Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Remove unused PM domains for PLLFilip Drazic2016-11-15-25/+0
| | | | | | | | | | | | Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: DT: Remove unused DDR PM domainFilip Drazic2016-11-15-5/+0
| | | | | | | | | | | | | | | | | | | | DDR power states are handled by the PM firmware, so this domain is redundant. Also, since there is no device using this PM domain, it will be powered off during boot, which is wrong. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove note about level shifter on zcu102Michal Simek2016-11-15-1/+1
| | | | | | | | | | | | i2c device is just level shifter. Remove reference from dts. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add dcc port to dtsiMichal Simek2016-11-15-0/+11
| | | | | | | | | | | | | | | | Add dcc to dtsi for supporting system without serial port. DCC is enabled by default on ZynqMP. Adding dcc to zcu100 and zcu102 which were tested. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add gpio-keys for zcu102Michal Simek2016-11-15-0/+15
| | | | | | | | | | | | | | There is gpio push button on MIO22. Add it to DTS to have full board description. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Enable gpio-led as heartbeat on zcu102Michal Simek2016-11-15-0/+9
| | | | | | | | | | | | Show user that Linux is alive on the board. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Enable can1 for ep108Naga Sureshkumar Relli2016-11-15-0/+8
| | | | | | | | | | | | | | | | This patch enables can1 for ep108. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Added clocks to DT for ep108VNSL Durga2016-11-15-0/+44
| | | | | | | | | | | | | | Added clks for ep108 platform. Signed-off-by: VNSL Durga <vnsldurg@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add clocks for LPDDMAKedareswara rao Appana2016-11-15-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | Zynqmp DMA driver expects two clocks (main clock and apb clock) LPDDMA clock cofiguration is missing for the same in the zynqmp-clk.dtsi file. This patch updates for the same. Reported-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Remove DTC 1.4.2 warningsMichal Simek2016-11-15-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba/usb@fe200000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/usb@fe300000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video2channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-graphicschannel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name This patch is fixing them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Remove DTC 1.4.2 warningsMichal Simek2016-11-15-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property This patch is fixing them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Correct the sdhci minimum frequency for ep108Siva Durga Prasad Paladugu2016-11-15-1/+1
| | | | | | | | | | | | | | | | Correct the sdhci minimum frequency for ep platform. It should be right shift instead of left shift operand. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Ignore warnings from autogenerated filesMichal Simek2016-11-15-0/+12
| | | | | | | | | | | | | | | | Autogenerated files contain casting issues and missing function declaration and even usleep implementation. Suppress them for now till these files are fixed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Fix secondary bootmode enablingMichal Simek2016-11-15-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Do not setup use_alt bit which copy alternative boot mode to boot mode. The reason is that this bit is cleared after POR but not after any software reset which will cause that after SW reset bootrom will look for different boot image. This patch setups alternative boot mode selection (purely SW handling) and extends code to read this alternative boot mode first and use it if it is setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add support for SD1 with level shifters bootmodeSiva Durga Prasad Paladugu2016-11-15-0/+4
| | | | | | | | | | | | | | Add support for SD1 with level shifters bootmode. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Record board name as serial number for DFU/FASTBOOTMichal Simek2016-11-15-0/+4
| | | | | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Adjust to new SMC interface to get silicon versionSoren Brinkmann2016-11-15-0/+17
| | | | | | | | | | | | | | | | | | | | The new FW interface returns the IDCODE and version register, leaving extracting bitfields to the caller. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Add support for Zynq 7000S 7007s/7012s/7014s devicesMichal Simek2016-11-15-0/+30
| | | | | | | | | | | | | | Zynq 7000S (Single A9 core) devices is using different ID code. This patch adds this new codes and assign them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | net: zynq_gem: Correct SGMII enable bit settingSiva Durga Prasad Paladugu2016-11-15-1/+1
| | | | | | | | | | | | | | | | | | Correct the SGMII enable bit position to 27 instead of 31. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: zynq_gem: Modify the nwcfg bit definitionsSiva Durga Prasad Paladugu2016-11-15-8/+8
| | | | | | | | | | | | | | | | | | Modify the nwcfg bit definitions to have 32-bit by removing the extra nibble. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | nand: arasan_nfc: Clear ecc on bit while sending read commandSiva Durga Prasad Paladugu2016-11-15-0/+2
| | | | | | | | | | | | | | | | | | | | Clear ecc ON bit while sending read command as all types of read command(like reading spare) doesnt need ECC to be enabled. It has been anyway taken care in other places whereever required using arasan_nand_enable_ecc(). Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynq: nand: Runtime detection of nand buswidth through slcrMichal Simek2016-11-15-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to check the buswidth on nand flash at runtime based on nand MIO configurations done by FSBL. User needs to correctly configure the MIO's based on the buswidth supported by the nand flash which is present on the board. Added nand8 and nand16 @periph names on slcr driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynq: nand: Enable Nand flash controller driver a zynq boardSiva Durga Prasad Paladugu2016-11-15-0/+9
| | | | | | | | | | | | | | | | Enable zynq Nand flash controller driver for a zynq ZC770 XM011(dc2) board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.1 at 2024-11-15 01:33:43 +0000