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* MLK-14474-1 pinctrl-imx: Fix wrong mask when SHARE_MUX_CONF_REG is setYe Li2017-04-05-1/+1
| | | | | | | when using SHARE_MUX_CONF_REG, wrong mask is used for writing config value. which causes mux value is cleared. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13925-1 mx7ulp_evk: Update LPDDR3 script to V1.4Ye Li2017-04-05-18/+4
| | | | | | | | | | | | | | | | | | | | Update LPDDR3 script from v1.2 to v1.4 EVK_IMX7ULP1_LPDDR3_320MHz_1GB_32bit_V1.4.inc with the changes below: Version 1.3 -Update the precharge command to CMD=01 at the DDR initialization phase Version 1.4 -remove unimplemented registers Write data bit delay --refer to the DDR_TRIM bits in IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn File: http://compass.freescale.net/livelink/livelink?func=ll&objid=235761218&objAction=browse&sort=name&viewType=1 Test: One EVK board passes overnight stress test. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit e3343cb38eac2cc69b58247b5adcb500e5f19834)
* MLK-13924 mx7ulp: Fix APLL num and denom setting issueYe Li2017-04-05-24/+1
| | | | | | | | | | | | | For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement. We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM, the NUM should always be less than the DENOM. So our setting violates the rule. Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock is 318.9888Mhz, which also meet the DDR requirement. To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 8cc70b1ded5309dee522aa00b43bd702a209ba51)
* MLK-13923 mx7ulp: Fix PCC register bits mask and offset issueYe Li2017-04-05-2/+2
| | | | | | | | The offset for FRAC and the mask for PCD are not correct. If we set FRAC, we can't get the right frequency. Fix them to correct value. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 079db9559c06c5e68ab8f6cd67ec4f5115dd2d59)
* MLK-13899 ARM: mx7ulp: Correct the clock index on imx7ulpBai Ping2017-04-05-1/+2
| | | | | | | | | On i.MX7ULP, value zero is reserved in SCG1 RCCR register, so the val should be decreased by 1 to get the correct clock source index. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 7c9a3573ec0191f1e0bea12956346a5eab2db43a)
* MLK-13761 board: imx7ulp: Fix system reset after a7 rtc alarm expired.Bai Ping2017-04-05-0/+7
| | | | | | | | | The board will reboot if A7 core enter mem mode by rtc, then M4 core enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode to fix this issue. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 5aa5974f487e0b4c2e963a86203161c5f05e2fdf)
* MLK-13776 ocotp: Add fuse word checking before programming it on i.MX7ULPYe Li2017-04-05-1/+19
| | | | | | | | | | | On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to write once, because they use ECC mode. Multiple writes may damage the ECC value and cause a wrong fuse value decoded when reading. This patch adds a checking before the fuse word programming, only can write when the word value is 0. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit e8447d649a631ec98120d84fab124ca29fbe39f0)
* MLK-13645 mx7ulp: Modify FDT file to disable SD3.0 for mfgtoolYe Li2017-04-05-0/+40
| | | | | | | | | | Since the SD3.0 kernel driver needs M4 image support, this causes problem to mfgtool. To decouple the relationship, we modify the FDT file in u-boot to disable SD3.0 when booting for mfgtool. So the kernel won't depend on M4 image. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit 1826d6e4dc732521190c742f812193be95eea211)
* MLK-13525-1 mx7ulp: Add common plugin codes for mx7ulpYe Li2017-04-05-1/+106
| | | | | | | | Add common plugin codes to call ROM's hwcnfg_setup and generate IVT2 header. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 58ffe85c25ff554c185d8f6fd8b6443f167227da)
* MLK-13450-17 sf: Add Macronix MX25R6435F SPI NOR flash to flash parameters arrayYe Li2017-04-05-0/+1
| | | | | | | On mx7ulp EVK board, we use MX25R6435F NOR flash, add its parameters and IDs to flash parameter array. Otherwise, the flash probe will fails. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-16 fsl_qspi: Update changes for mx7ulpYe Li2017-04-05-1/+24
| | | | | | | | | | | | The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes) than other i.MX. Change some parameters for it. Also found when the DDR_EN bit is set, sometime the page programming will fail during large data programming. The 64 bytes data is not programmed into flash. But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue. We have disable the DDR_EN for mx7ulp. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-15 ehci-mx6: Add powerup_fixup implementationYe Li2017-04-05-1/+27
| | | | | | | | | | | | | | | | | | | | | When doing port reset, the PR bit of PORTSC1 will be automatically cleared by our IP, but standard EHCI needs explicit clear by software. The EHCI-HCD driver follow the EHCI specification, so after 50ms wait, it clear the PR bit by writting to the PORTSC1 register with value loaded before setting PR. This sequence is ok for our IP when the delay time is exact. But when the timer is slower, some bits like PE, PSPD have been set by controller automatically after the PR is automatically cleared. So the writing to the PORTSC1 will overwrite these bits set by controller. And eventually the driver gets wrong status. We implement the powerup_fixup operation which delays 50ms and will check the PR until it is cleared by controller. And will update the reg value which is written to PORTSC register by EHCI-HCD driver. This is much safer than depending on the delay time to be accurate and aligining with controller's behaiver. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 8dfdf83abaff44efb487f801cd1757a729d427c5)
* MLK-13450-14 ehci-mx6: Update EHCI driver to support OTG0 on i.MX7ULPYe Li2017-04-05-15/+42
| | | | | | | | | | | | The ULP has two USB controllers. These two controllers have similar NC registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY to work. This patch only supports OTG0 with UTMI PHY. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 1ac22cabb96a14ac4ca58df60ae2025fb5e94db6)
* MLK-13450-7 mx7ulp: Add M4 core boot support when using single boot modeYe Li2017-04-05-0/+75
| | | | | | | | | | | | | | | | | | | The single boot mode in MX7ULP will only boot up A7, the M4 is running in ROM by checking entry from SIM0 GP register. In this patch, We bind M4 image with u-boot.bin by allocating a section for m4 image. So the whole image (included M4 image) will be loaded by A7 ROM into DDR. Then when u-boot is up, it will try to load M4 image into TCML and boot it there. Since M4 image will not be relocated in u-boot codes, we must load it during board_f. Current implementation put it in arch_cpu_init to get M4 booted as quick as possible. We requires the M4 image with IVT head and padding embedded, not a RAW binary. The image should be same as what is used for M4 QSPI boot in dual boot mode. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 04163dbd4f6190f310fff17b53b4bc7b8370ba89)
* imx: mx7ulp_evk: enable mmc/regulator supportPeng Fan2017-04-05-1/+106
| | | | | | | | | | | Enable MMC support. The fsl sdhc driver needs regulator to enable power, so enable regulator support. And bootcmd and more env. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: imx7ulp: add EVK board supportPeng Fan2017-04-05-0/+1064
| | | | | | | | | | | | | | | | | | | | | | | | Add EVK board support. Add the evk dts file. LOG: U-Boot 2017.03-rc2-00038-gab86c1d (Feb 22 2017 - 15:59:58 +0800) CPU: Freescale i.MX7ULP rev1.0 at 500 MHz Reset cause: POR Boot mode: Dual boot Model: NXP i.MX7ULP EVK DRAM: 1 GiB MMC: FSL_SDHC: 0 In: serial@402D0000 Out: serial@402D0000 Err: serial@402D0000 Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* mmc: fsl_esdhc: support i.MX7ULPPeng Fan2017-04-05-0/+8
| | | | | | | | | Add compatible property for i.MX7ULP. Add a weak init_usdhc_clk function, i.MX7ULP use this to init the clock. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
* arm: dts: add i.MX7ULP dtsi filePeng Fan2017-04-05-0/+1641
| | | | | | | | Add i.MX7ULP dtsi file. Add clock and pinfun header files. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* mx7ulp: Add HAB boot supportPeng Fan2017-04-05-1/+21
| | | | | | | | | | | | Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF size for HAB support boot on mx7ulp. Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build secure uboot. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
* serial: lpuart: add i.MX7ULP supportPeng Fan2017-04-05-9/+176
| | | | | | | | | | | | | | Add i.MX7ULP support. The buadrate calculation on i.MX7ULP is different,so add a new setbrg function for i.MX7ULP. Add a enum lpuart_devtype for runtime check for different platforms. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: York Sun <york.sun@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@nxp.com> Cc: Alison Wang <b18965@freescale.com>
* serial: lpuart: restructure lpuart driverPeng Fan2017-04-05-235/+148
| | | | | | | | | | | | | | | | Drop CONFIG_LPUART_32B_REG. Move the register structure to a common file include/fsl_lpuart.h Define lpuart_serial_platdata structure which includes the reg base and flags. For 32Bit register access, use lpuart_read32/lpuart_write32 which handles big/little endian. For 8Bit register access, still use the orignal code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: York Sun <york.sun@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@nxp.com> Cc: Alison Wang <b18965@freescale.com>
* i2c: lpi2c: add lpi2c driver for i.MX7ULPPeng Fan2017-04-05-0/+989
| | | | | | | | | | | Add lpi2c driver for i.MX7ULP. Need to enable the two options to use this driver: CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* pinctrl: Add i.MX7ULP pinctrl driverPeng Fan2017-04-05-4/+65
| | | | | | | | | Add i.MX7ULP pinctrl driver. Select CONFIG_PINCTRL_IMX7ULP to use this driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by : Stefano Babic <sbabic@denx.de>
* wdog: Add the watchdog driver for MX7ULP.Ye Li2017-04-05-0/+107
| | | | | | | | | | | | | This driver implements the HW WATCHDOG functions. Which needs to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for mx7ulp. Use watchdog for reset cpu. Implement this in the driver. Need to define CONFIG_ULP_WATCHDOG to build it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* mx7ulp: Add iomux pins header fileYe Li2017-04-05-0/+910
| | | | | | | | | | | | | Add the iomux pins header file from iomux tool team. Change the IOMUXC0 pins to add IOMUX_CONFIG_MPORTS flags. Note: The IOMUXC0 offset provided in this file is from 0xD000, this is not aligned with IOMUXC0 base address. We have adjusted the IOMUXC0 base address to aligin with it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULPPeng Fan2017-04-05-1/+53
| | | | | | | | | | | | | Update the mxc_ocotp driver to support i.MX7ULP. The read/write sequence has some changes due to PDN and OUT_STATUS registers added and TIME register is removed. Also update the bank size and number. Add is_mx7ulp macro in sys_proto.h Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
* gpio: Add Rapid GPIO2P driver for i.MX7ULPPeng Fan2017-04-05-0/+254
| | | | | | | | | | | | | | | | | Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP. Have added all ports on RGPIO2P_0 and RGPIO2P_1. The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set to y to enable the drivers. To use the GPIO function, the IBE and OBE needs to set in IOMUXC. We did not set the bits in driver, but leave them to IOMUXC settings of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number for gpio APIs access. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
* imx: mx7ulp: Implement the clock functions for i2c driverYe Li2017-04-05-0/+44
| | | | | | | | | Implement the i2c clock enable and get function for mx7ulp. These functions are required by imx_lpi2c driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx7ulp: Add soc level initialization codes and functionsPeng Fan2017-04-05-2/+268
| | | | | | | | | | | | | | | Implement soc level functions to get cpu rev, reset cause, enable cache, etc. We will disable the wdog and init clocks in s_init at very early u-boot phase. Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev is hard coded to a fixed value. This may change in future. Reuse some code in imx-common. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx7ulp: Add clock framework and functionsPeng Fan2017-04-05-1/+2441
| | | | | | | | | | | | | | | | | | Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set clock source, divider, clock rate and parent source. Users need to include pcc.h to use the APIs to for peripherals clock. Each peripheral clock is defined in enum pcc_clk type. SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD enablement and settings, and all SCG clock initialization. User need use enum scg_clk to access each clock source. In clock.c, we initialize necessary clocks at u-boot s_init and implement the clock functions used by driver modules to operate clocks dynamically. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1Peng Fan2017-04-05-0/+173
| | | | | | | | | | | | Add a new driver under ULP directory to support its IOMUXC controllers. The ULP has two IOMUXC, the IOMUXC0 is used for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as the default IOMUX in this driver. Any pins in IOMUXC0 needs to configure with IOMUX_CONFIG_MPORTS in its mux_mode field. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
* imx: mx7ulp: add registers header filePeng Fan2017-04-05-0/+1120
| | | | | | | | | Add imx-regs.h for i.MX7ULP registers addresses definitions and some registers structures. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
* imx: mx7ulp: Add mx7ulp to KconfigPeng Fan2017-04-05-1/+15
| | | | | | | | | | i.MX7ULP is a new series SoC which has different architecture from previous i.MX platforms. Create a new cpu folder for it, and add it to Kconfig. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
* MLK-14419-3 imx: mx7d_arm2: add 19x19 LPDDR2/LPDDR3/DDR3 ARM2 supportPeng Fan2017-04-05-1/+5032
| | | | | | | | | Add 19x19 LPDDR2/LPDDR3/DDR3 ARM2 board supports. Enable the OF_CONTROL and convert them to use DM driver. Since the DTB lacks the support for some modules. We have to use QSPI and FEC with non-DM driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14419-2 imx: mx7d_arm2: add 12x12 ddr3 arm2 board supportPeng Fan2017-04-05-0/+1374
| | | | | | | | Add 12x12 ddr3 arm2 board support and convert it to use OF_CONTROL and DM drivers. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14419-1 imx: mx7d_arm2: add 12x12 lpddr3 arm2 supportPeng Fan2017-04-05-1/+3371
| | | | | | | | Add mx7d 12x12 lpddr3 arm2 support, which has enabled the OF_CONTROL and DM drivers Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14418-13 imx: mx7dsabresd: Update Misc codesYe Li2017-04-05-9/+26
| | | | | | | | 1. Add BMODE support 2. Update environment variables to align with v2016.03 3. Remove the wdog WCR bit 4 clear. Since we have implemented reset_cpu for mx7d. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14418-12 imx: mx7dsabresd: Update LCD splash screen codesYe Li2017-04-05-10/+27
| | | | | | | Update LCD setup codes to use the parameters structure used for all i.mx platforms, discard to use videmode environment variable. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14418-11 imx: mx7dsabresd: add reva/revb config filePeng Fan2017-04-05-0/+144
| | | | | | Add reva/revb config file. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-14418-10 imx: mx7dsabresd: update ddr script and add plugin supportPeng Fan2017-04-05-0/+433
| | | | | | Update ddr script and add plugin support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-14418-9 imx: mx7dsabresd: add nand/qspi boot supportPeng Fan2017-04-05-27/+282
| | | | | | | | | | Add nand/qspi build configurations for their boot support. Also Add gpmi-nand and qspi specified DTS files for enable them. For QSPI, this patch changes it to use DM driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14418-8 imx: mx7dsabresd: add epdc supportPeng Fan2017-04-05-0/+398
| | | | | | | | Add epdc support from v2016.03. Add a epdc specified DTS file for using epdc Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14418-7 imx: mx7dsabresd: add FEC DM supportPeng Fan2017-04-05-51/+104
| | | | | | | | Add FEC2 and convert to use FEC DM driver. Add board rev check. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14418-6 imx: mx7dsabresd: switch to DM USBPeng Fan2017-04-05-28/+3
| | | | | | Switch to use DM USB. Enable GPIO regulator to handle vbus supply. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-14418-5 imx: mx7dsabresd: reset ENET_RST_BPeng Fan2017-04-05-0/+16
| | | | | | | | Reset ENET_RST_B to make ENET function stable. Since DM_GPIO enabled, we use "gpio_spi@0_5" which corresponds to ENET_RST_B. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-14418-4 imx: mx7dsabresd: enable dm driversPeng Fan2017-04-05-267/+32
| | | | | | | Enable GPIO/I2C/MMC/SPI/74X164 DM drivers. Discard mxc spi support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-14418-3 imx: mx7: Enable dtb support for mx7dsabresdPeng Fan2017-04-05-2/+5
| | | | | | Enable dtb support for mx7dsabresd board. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-14418-2 configs: mx7dsdb: rename board config filePeng Fan2017-04-05-5/+5
| | | | | | Let kernel default runs in secure mode. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-14418-1 imx: mx7: introduce dts filesPeng Fan2017-04-05-54/+3279
| | | | | | | Introduce dts files for i.MX 7D SabreSD platform. From imx_4.1.y, based on "commit b423f954fb755" Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12425-6: mx7: add epdc qos settingsPeng Fan2017-04-05-1/+32
| | | | | | | | This EPDC/EPXP QoS setting is needed for EPDC stress test to pass. Signed-off-by: Robby Cai <r63905@freescale.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 1b32518d1c27f05eb84a4cb93594710354b2e343)
generated by cgit v1.1 at 2024-11-09 10:06:29 +0000