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authorPeng Fan <peng.fan@nxp.com>2016-02-23 10:12:20 +0800
committerYe Li <ye.li@nxp.com>2017-04-05 14:07:05 +0800
commit8fd2dbe9097b09715f84e1c0c17dcd6a6351fb35 (patch)
tree74856721479152c3de5f12080f4471c9a10289e9
parent62d2c94a9bf0c8ef6a9d5c712af78cb0056fc54d (diff)
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MLK-12425-6: mx7: add epdc qos settings
This EPDC/EPXP QoS setting is needed for EPDC stress test to pass. Signed-off-by: Robby Cai <r63905@freescale.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 1b32518d1c27f05eb84a4cb93594710354b2e343)
-rw-r--r--arch/arm/cpu/armv7/mx7/soc.c33
1 files changed, 32 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
index 2796ba3..8202145 100644
--- a/arch/arm/cpu/armv7/mx7/soc.c
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
@@ -229,6 +229,35 @@ static void imx_enet_mdio_fixup(void)
}
}
+static void set_epdc_qos(void)
+{
+#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR
+#define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400)
+#define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00)
+#define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00)
+
+ writel(0, REGS_QOS_BASE); /* Disable clkgate & soft_reset */
+ writel(0, REGS_QOS_BASE + 0x60); /* Enable all masters */
+ writel(0, REGS_QOS_EPDC); /* Disable clkgate & soft_reset */
+ writel(0, REGS_QOS_PXP0); /* Disable clkgate & soft_reset */
+ writel(0, REGS_QOS_PXP1); /* Disable clkgate & soft_reset */
+
+ writel(0x0f020722, REGS_QOS_EPDC + 0xd0); /* WR, init = 7 with red flag */
+ writel(0x0f020722, REGS_QOS_EPDC + 0xe0); /* RD, init = 7 with red flag */
+
+ writel(1, REGS_QOS_PXP0); /* OT_CTRL_EN =1 */
+ writel(1, REGS_QOS_PXP1); /* OT_CTRL_EN =1 */
+
+ writel(0x0f020222, REGS_QOS_PXP0 + 0x50); /* WR, init = 2 with red flag */
+ writel(0x0f020222, REGS_QOS_PXP1 + 0x50); /* WR, init = 2 with red flag */
+ writel(0x0f020222, REGS_QOS_PXP0 + 0x60); /* rD, init = 2 with red flag */
+ writel(0x0f020222, REGS_QOS_PXP1 + 0x60); /* rD, init = 2 with red flag */
+ writel(0x0f020422, REGS_QOS_PXP0 + 0x70); /* tOTAL, init = 4 with red flag */
+ writel(0x0f020422, REGS_QOS_PXP1 + 0x70); /* TOTAL, init = 4 with red flag */
+
+ writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034); /* EPDC AW/AR CACHE ENABLE */
+}
+
int arch_cpu_init(void)
{
init_aips();
@@ -239,6 +268,8 @@ int arch_cpu_init(void)
imx_enet_mdio_fixup();
+ set_epdc_qos();
+
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */
mxs_dma_init();