| Commit message (Collapse) | Author | Age | Lines |
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Change the i2c alias seq number to align with device index. So in lpi2c
driver we don't need to add 4 to get the device index. This codes may not
valid on other platforms.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The MX6SL, SLL and ULL have DCP to replace CAAM in SoC. We have to
disable the CAAM driver for them.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Modify the CONFIG_CSF_SIZE to 0x4000 to align with v2016.03. Also remove
the duplicated setting for CSF size.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The num/denom is a float value, but in the calculation it is convert
to integer 0, and cause the result wrong.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 4a8f51499ca098637e9ee2036066374d34458865)
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According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit
is set to 1 before the caches and MMU are enabled, or any cache and TLB
maintenance operations are performed".
ROM sets this bit in normal boot flow, but when in serial download mode, it is not set.
Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms,
including mx7d, mx6ul/ull and mx7ulp.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 14990af03450f3e1898135c86fd8b93328007617)
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To improve the performance, enable the bank interleave for DDR3. Update
the DDR3 settings to new script IMX7D_DDR3_533MHz_1GB_32bit_V2.0.ds
Changes:
1. Enable bank interleave
2. Improve the drive strength for non-TO1.1 chips.
3. Updates ZQ_CON0 settings.
4. For 19x19 DDR3 ARM2 and 12x12 DDR3 ARM2, they are using old version scripts which
were not upgrade with SABRESD script. According to DDR owner suggestion, to use same version
script for all of them.
File:
http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1
Test:
Passed stress test on one TO1.2 SABRESD, one TO1.1 SABRESD and one TO1.0 SABRESD.
Passed stress test on one 12x12 ddr3 ARM2.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 62e73b45c53e3302d869c373da72699199b90648)
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To improve the performance, enable the bank interleave for LPDDR3. Update
the LPDDR3 settings to new script IMX7D_LPDDR3_533MHz_2GB_32bit_V2.0.ds5.
Changes:
1. Enable bank interleave
2. Improve the drive strength for non-TO1.1 chips.
3. Updates ZQ_CON0 settings.
4. Change to 0 for reserved bits.
File:
http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1
Test:
Passed stress test on one 19x19 lpddr3 arm2 and one 12x12 lpddr3 arm2.
Passed LPSR test on one 12x12 lpddr3 arm2.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 9a4fa3f8d2762791a76fd90e83feec8c8c9235b0)
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Update lpddr2 settings to latest version
IMX6UL_LPDDR2_400MHz_16bit_V1.1.inc
Use pre-charge command 0x1 per DDR register programming aid
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit e7aa25c2c7313b00475e3e0ce394a2fbaa569fbd)
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Update lpddr2 settings to latest version
MX6SL_MMDC_LPDDR2_register_programming_aid_v0.9.inc
Use pre-charge command 0x1 per DDR register programming aid
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit 7c15f3afbd2cfa97b14a0013ef959e9e73fd2f1e)
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LPDDR2 script MX6SL_MMDC_LPDDR2_register_programming_aid_v0.9.inc
Updated to add Precharge all command per JEDEC
The memory controller may optionally issue a precharge-all command
prior to the MRW reset command
This is strongly recommended to ensure robust DRAM initialization
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 498f4a791593069220213c6d777527f4d899fb8a)
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- Adjust ZQ delay for MMDC clock frequency at 400MHz
- Precharge all commands per JEDEC
The memory controller may optionally issue a Precharge-All command
prior to the MRW Reset command, this is strongly recommended to ensure
a robust DRAM initialization
DDR Calibration script:
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/a72e010a1fd8c7fe0fda7bdc4d058c478e94c3da
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit 03cc626df73d6c2bb36daf280b1cd43170c298a0)
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Add fastboot and recovery mode support for mx6qarm
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit 505e899ce582118da28ca1f4487ce7f179225bd7)
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Add Android support for mx6qarm2 lpddr2 pop target
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit 6356f2b420f3571493755f6b3a307a66a539b60c)
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1. pass androidboot.storage_type to android, 'init' use it to parse
different init.freescale.storage.rc.
2. store new ptable with gpt partition.
3. we use the last LBA as backup gpt table, there is many warning log
when boot, change print to debug
Change-Id: I84070735e9d4c2741b0e240bc1c61b357dabc5b8
Signed-off-by: Sanshan Zhang <sanshan.zhang@nxp.com>
(cherry picked from commit da0ce2787256a323371641b0764266d386d767a5)
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add android features on i.MX7ULP EVK board.
Implement the code to get boot device and the serial number on mx7ulp.
TODO: will add the code which check misc partition after porting BCB.
Change-Id: I9d06fecba303fa4dfdcaf73da1b6246444697bba
Signed-off-by: Sanshan Zhang <sanshan.zhang@nxp.com>
(cherry picked from commit 4c60cba3a017b921aebb84dd1268c898e549c99a)
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add board level support for android fastboot feature. Each board has
a android specified header file for defining android related configuraitons.
And add build targets for their android uboot images building.
For mx6qsabreauto, mx6sabresd and mx7dsabresd, we enable the android
fastboot exclusive with DFU.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 43fe988af28c5e51fb23aa846e04bc9698256926)
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Integrate the FSL android fastboot features into community's fastboot.
1. Use USB gadget g_dnl driver
2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and
EFI partitions are not support by i.MX.
3. Add FDT support to community's android image.
4. Add a new boot command "boota" for android image boot. The boota
implements to load ramdisk and fdt to their loading addresses
specified in boot.img header, while bootm won't do it for android image.
5. Support the authentication of boot.img at the "load_addr" for
both SD and NAND.
6. We use new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot
with relevant header file "fsl_fastboot.h". While disabling the
configuration, the community fastboot is used.
7. Overwrite the cmdline in boot.img by using bootargs saved in local environment.
8. Add recovery and reboot-bootloader support.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 23d63ff185929fff5e392efc853d69b606ba081a)
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The i.MX6SL EVK needs this driver in android fastboot support. Add
this driver to u-boot.
To use the driver, user must define:
CONFIG_MXC_KPD Enable the driver
CONFIG_MXC_KEYMAPPING Key mapping matrix
CONFIG_MXC_KPD_COLMAX The column size of key mapping matrix
CONFIG_MXC_KPD_ROWMAX The row size of the key mapping matrix
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5096e572667ff41217deb4ba9b1bd15e93fa6b59)
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After changed to USB DM driver, the framework uses the seq to find usb
device when registering a gadget driver. We have to add usb0 alias in
all i.MX6 and i.MX7 dtsi, otherwise the gadget driver register will fail.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add the 10x10 ARM2 and 14x14 ARM2 DTS files. Also convert the board
codes to use OF_CONTROL and DM drivers.
Since the DTS files only have UART and SD1 supported. So we only enable
the DM for these two modules. QSPI and USB are still kept in non-DM fashion.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Copy the mx7ulp ARM2 codes from v2016.03 as the base for using
OF_CONTROL and DM drivers.
The 14x14 ARM2 LPDDR3 script is v1.5:
- IMX7ULP1_LPDDR3_320MHz_512MB_32bit_V1.5.inc
The 10x10 ARM2 LPDDR2 script is v1.1:
- IMX7ULP1_LPDDR2_320MHz_1GB_32bit_V1.1.inc
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add MT35XU512ABA parameters to NOR flash parameters array. Since the
manufactory ID is changed to 0x2C, add it for micron and using it for
relevant settings.
The MT35XU512ABA only supports 1 bit mode and 8 bits. It can't support
dual and quad. Because the 8 bits is not support by u-boot framework and
driver. We only use 1 bit mode for this flash.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add environment variables for mfgtool.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add the OCOTP driver and fuse command configurations.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add build configuration and DTS file to enable eMMC for eMMC reworked
EVK board.
Because the eMMC DTS file has QSPI node disabled, so we change to use
non-DM QSPI driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add board_late_mmc_env_init to support MMC device detection for environment
variables.
Signed-off-by: Ye Li <ye.li@nxp.com>
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PTA and PTB banks are at M4 domain, but some boards like ARM2 use
them for controlling A7 domain modules. So we may need to support
them in GPIO driver.
In the imx_rgpio2p driver, the non-DM driver supports full 6 GPIO
banks, with PTA from index 0. But the DM driver which uses DTB only
have 4 GPIO banks, with PTC from index 0.
This will cause problem when using GPIO. So this patch add PTA and PTB
banks to DTB, and reorder the sequence for gpio with PTA from index 0.
So the non-DM driver and DM driver are aligned.
Signed-off-by: Ye Li <ye.li@nxp.com>
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u-boot has feature that when booting for mfgtool, the u-boot will modify the DTB
to disable SD 1.8v switch. But the judgement for mfgtool boot has a problem, it
only checks whether the USB PHY power status is enabled. When a USB device
(for example a USB ethernet) is used in u-boot, the power status is also enabled.
So the u-boot incorrectly disable the SD 1.8v switch.
The patch changes the get_boot_device to use the boot SW info provided by ROM. Only if
it is a USB boot, we will start the DTB modification for SD.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 1fb61cd80af59c39d1ca01d833f566628ba48f32)
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Since we can use USB ethernet instead of local ethernet, add ethernet support
for it. To use USB ethernet function at u-boot, just plug in Micro-AB cable
at USBOTG1 port with USB2Ethernet adapter connected.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
(cherry picked from commit 60ffddf87cf6b8502c5d5fc6540364adfd66ebb3)
Signed-off-by: Ye Li <ye.li@nxp.com>
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Enable and setup board level codes for MIPI DSI splashscreen on EVK board.
User needs set env variable"panel=HX8363_WVGA" for displaying.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 49cb68f5c17e42f9290336e1252ace6ac7d0b5ce)
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Add the clocks functions for enabling LCDIF and DSI clocks.
Also add the arch_preboot_os to disable the video before enter into
the kernel.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit a783799017a929f9918c9c5981fe3a7a25cd8125)
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Update the registers base address and LCDIF registers structure for
mx7ulp.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 29a2032fc0c2330718dbab1f96c1201ae5b49b6f)
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The LCDIF provides video source for MIPI DSI host at DPI-2 interface.
When the LCDIF Framebuffer driver is enabled, it uses the panel
parameters setup by environments to create a panel device and register
it to DSI host driver and then enable the DSI host.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 85659ea5ee975fa2d5fa7215e17a01f7006c39bf)
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Add the mipi dsi panel driver for device HX8363 from kernel. The panel
driver needs work with mipi_dsi_northwest driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 0c6d0f4202bae7f61d38ecff1c9d255261f022f2)
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Add the host driver base from kernel for MIPI DSI controller on i.MX7ULP.
The controller provides a DPI-2 interface for LCDIF video stream, and a APB interface
for packet transmission.
The driver provides APIs to register a MIPI panel device and its driver. The panel
driver can use the write packet function provided by the host driver to send control
packets to panel device via APB interface.
MIPI DSI has its PHY and dedicated PLL. The driver will setup them when enabling the DSI
host.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e02115dd1c5d36ec06eabcb5a0b8e09aaf0f29a0)
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Porting codes to support USB OTG0 on the EVK board. Convert
to use DM USB driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The i.MX7ulp EVK board uses GPIO to detect ID for USB OTG0,
but when using DM USB driver, it is hard coded to use OTG ID pin.
Add a board override function that when extcon property is provided,
the function can check the GPIO to get ID.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Wrong I2c driver configuration name is used in codes, so I2c driver is
not built. Correct it.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Enable the CONFIG_ULP_WATCHDOG in defconfig, so that reset command
can work.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Porting the QSPI flash board support from v2016.03, and convert to use
DM QSPI driver.
Since we need to support QSPI at default in u-boot, change the default
DTS file to qspi enabled DTS.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Since many drivers need this CONFIG_MX7ULP to distiguish the settings
for i.MX7ULP only. Add this entry to cpu's kconfig.
Signed-off-by: Ye Li <ye.li@nxp.com>
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In mx7ulp pinctrl driver, we should create two info instances for
iomuxc0 and iomuxc1 respective, otherwise they will share the same
info instance, and cause problem in get base address... etc.
Signed-off-by: Ye Li <ye.li@nxp.com>
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when using SHARE_MUX_CONF_REG, wrong mask is used for writing config value.
which causes mux value is cleared.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Update LPDDR3 script from v1.2 to v1.4 EVK_IMX7ULP1_LPDDR3_320MHz_1GB_32bit_V1.4.inc
with the changes below:
Version 1.3
-Update the precharge command to CMD=01 at the DDR initialization phase
Version 1.4
-remove unimplemented registers
Write data bit delay --refer to the DDR_TRIM bits in IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn
File:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235761218&objAction=browse&sort=name&viewType=1
Test:
One EVK board passes overnight stress test.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e3343cb38eac2cc69b58247b5adcb500e5f19834)
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For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement.
We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM,
the NUM should always be less than the DENOM. So our setting violates the rule.
Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock
is 318.9888Mhz, which also meet the DDR requirement.
To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 8cc70b1ded5309dee522aa00b43bd702a209ba51)
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The offset for FRAC and the mask for PCD are not correct. If we set FRAC, we
can't get the right frequency. Fix them to correct value.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 079db9559c06c5e68ab8f6cd67ec4f5115dd2d59)
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On i.MX7ULP, value zero is reserved in SCG1 RCCR register,
so the val should be decreased by 1 to get the correct clock
source index.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 7c9a3573ec0191f1e0bea12956346a5eab2db43a)
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The board will reboot if A7 core enter mem mode by rtc, then M4 core
enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode
to fix this issue.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 5aa5974f487e0b4c2e963a86203161c5f05e2fdf)
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On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to write once,
because they use ECC mode. Multiple writes may damage the ECC value and cause a
wrong fuse value decoded when reading.
This patch adds a checking before the fuse word programming, only can write
when the word value is 0.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e8447d649a631ec98120d84fab124ca29fbe39f0)
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Since the SD3.0 kernel driver needs M4 image support, this causes problem to mfgtool.
To decouple the relationship, we modify the FDT file in u-boot to disable
SD3.0 when booting for mfgtool. So the kernel won't depend on M4 image.
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 1826d6e4dc732521190c742f812193be95eea211)
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