diff options
| author | Ye Li <ye.li@nxp.com> | 2017-02-15 17:34:10 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 17:24:35 +0800 |
| commit | d9c18658e20ad8cca6f1d1fda39c2c0b8f4fed95 (patch) | |
| tree | f7647c48620e76b377a1d7925017aadaf7288feb | |
| parent | 7ef1d78154fef4f799dbf7de0f3d9679911ffa39 (diff) | |
| download | u-boot-imx-d9c18658e20ad8cca6f1d1fda39c2c0b8f4fed95.zip u-boot-imx-d9c18658e20ad8cca6f1d1fda39c2c0b8f4fed95.tar.gz u-boot-imx-d9c18658e20ad8cca6f1d1fda39c2c0b8f4fed95.tar.bz2 | |
MLK-13929-4 mx7ulp: Update registers and memory map for DSI and LCDIF
Update the registers base address and LCDIF registers structure for
mx7ulp.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 29a2032fc0c2330718dbab1f96c1201ae5b49b6f)
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 9 | ||||
| -rw-r--r-- | arch/arm/include/asm/imx-common/regs-lcdif.h | 9 |
2 files changed, 14 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index a9b7c87..ecc7218 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -62,6 +63,8 @@ #define SIM1_PCC1_SLOT (48) #define MMDC0_AIPS3_SLOT (43) #define IOMUXC_DDR_AIPS3_SLOT (45) +#define DSI_AIPS3_SLOT (41) +#define LCDIF_AIPS3_SLOT (42) #define LPI2C0_AIPS0_SLOT (51) #define LPI2C1_AIPS0_SLOT (52) @@ -175,6 +178,10 @@ #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) +#define DSI_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * DSI_AIPS3_SLOT))) +#define LCDIF_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LCDIF_AIPS3_SLOT))) +#define MXS_LCDIF_BASE LCDIF_RBASE + #define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT))) #define SNVS_LP_LPCR (SNVS_BASE + 0x38) @@ -940,6 +947,8 @@ #define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL)) #define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL)) +#include <asm/imx-common/regs-lcdif.h> + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> diff --git a/arch/arm/include/asm/imx-common/regs-lcdif.h b/arch/arm/include/asm/imx-common/regs-lcdif.h index ab147b5..cae157c 100644 --- a/arch/arm/include/asm/imx-common/regs-lcdif.h +++ b/arch/arm/include/asm/imx-common/regs-lcdif.h @@ -5,7 +5,8 @@ * on behalf of DENX Software Engineering GmbH * * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -20,7 +21,7 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */ mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */ #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) + defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || defined(CONFIG_MX7ULP) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ @@ -56,7 +57,7 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ #if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ - defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) + defined(CONFIG_MX7) || defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || defined(CONFIG_MX7ULP) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ @@ -65,7 +66,7 @@ struct mxs_lcdif_regs { mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */ mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */ #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7) || \ - defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) + defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || defined(CONFIG_MX7ULP) mxs_reg_32(hw_lcdif_thres) mxs_reg_32(hw_lcdif_as_ctrl) mxs_reg_32(hw_lcdif_as_buf) |