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* ARM: UniPhier: add I/O pin settings for xHCI on PH1-Pro4Masahiro Yamada2015-03-01-0/+7
| | | | | | This is necessary to use the xHCI cores for PH1-Pro4. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: replace "usb-ehci" with "generic-ehci"Masahiro Yamada2015-03-01-16/+16
| | | | | | | EHCI host controllers have a common register interface. We may wish to implement a generic EHCI driver someday. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: move uniphier_ehci_reset() functionMasahiro Yamada2015-03-01-28/+14
| | | | | | | | Because uniphier_ehci_reset() is only called from ehci-uniphier.c, it can be a static function there. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
* ARM: UniPhier: remove EHCI platform devicesMasahiro Yamada2015-03-01-59/+6
| | | | | | | | | | | Now UniPhier platform highly depends on Device Tree configuration (CONFIG_OF_CONTROL is select'ed by Kconfig). Since the EHCI is only used on main U-Boot, we can drop platform devices of the EHCI controllers. We still keep UART platform devices because they might be useful for SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
* ARM: UniPhier: enable STDMAC for EHCIMasahiro Yamada2015-03-01-2/+10
| | | | | | | Deassert the reset signal and provide the clock for STDMAC core. This is necessary for the USB 2.0 host controllers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: reset NAND core in SPL for non-NAND boot modeMasahiro Yamada2015-03-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | For all the UniPhier SoCs so far, the reset signal of the NAND core is automatically deasserted after the PLL gets stabled. (The bit 2 of SC_RSTCTRL is default to one.) This causes a fatal problem on the NAND controller of PH1-LD4. For that SoC, the NAND I/O pins are not set up yet at the power-on reset except the NAND boot mode. As a result, the NAND controller begins automatic device scanning with wrong I/O pins and finally hangs up. Actually, U-Boot dies after printing "NAND:" on the console unless the boot mode latch detected the NAND boot mode. To work around this problem, reset the NAND core in SPL for non-NAND boot modes. If CONFIG_NAND_DENALI is enabled, the reset signal is deasserted again in U-Boot proper. At this time, I/O pins have been correctly set up, the device scanning should succeed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: split clkrst_init() into two functionsMasahiro Yamada2015-03-01-49/+74
| | | | | | | | | | | | | | Split the current clkrst_init() into two functions: - early_clkrst_init(): called from SPL Deassert the reset signals of the memory controller and some other basic cores. - clkrst_init(): called from main U-boot Deassert the reset signals that are necessary for the access to peripherals etc. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*Masahiro Yamada2015-03-01-13/+13
| | | | | | Follow the register macros in the LSI specification book. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: fix SBC init codeMasahiro Yamada2015-03-01-25/+24
| | | | | | | | | Now UniPhier SoCs only work with CONFIG_SPL and the function sbc_init() is called from SPL. The conditional #if !defined(CONFIG_SPL_BUILD) has no point any more. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: fix comments in PH1-Pro4 SBC codeMasahiro Yamada2015-03-01-3/+3
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* serial: UniPhier: move LCR register setting to probe functionMasahiro Yamada2015-03-01-9/+11
| | | | | | | We do not have to set the LCR register every time we change the baud-rate. We just need to set it up once in the probe function. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* serial: UniPhier: use 32 bit register accessMasahiro Yamada2015-03-01-28/+26
| | | | | | | | For PH1-Pro4, the 8 bit write access to LCR register (offset = 0x11) is not working correctly. As a side effect, it also modifies MCR register (offset = 0x10) and results in unexpected behavior. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: update defconfigs using savedefconfigMasahiro Yamada2015-03-01-27/+27
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>Masahiro Yamada2015-03-01-69/+69
| | | | | | | | | Since commit 0e7368c6c426 (kbuild: prepare for moving headers into mach-*/include/mach), we can replace #include <asm/arch/*.h> with <mach/*.h> so we do not need to create the symbolic link during the build. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: move SoC headers to mach-uniphier/include/machMasahiro Yamada2015-03-01-1/+0
| | | | | | | Move arch/arm/include/asm/arch-uniphier/* -> arch/arm/mach-uniphier/include/mach/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: move SoC sources to mach-uniphierMasahiro Yamada2015-03-01-3/+3
| | | | | | | Move arch/arm/cpu/armv7/uniphier/* -> arch/arm/mach-uniphier/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-02-25-334/+2404
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| * crypto/fsl - Add progressive hashing support using hardware acceleration.gaurav rana2015-02-25-7/+302
| | | | | | | | | | | | | | | | | | | | | | Currently only normal hashing is supported using hardware acceleration. Added support for progressive hashing using hardware. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <yorksun@freescale.com>
| * crypto/fsl: Make function names consistent for blob encapsulation/decapsulation.gaurav rana2015-02-25-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: 1. The function names for encapsulation and decapsulation were inconsitent in freescale's implementation and cmd_blob file. This patch corrects the issues. 2. The function protopye is also modified to change the length parameter from u8 to u32 to allow encapsulation and decapsulation of larger images. 3. Modified the description of km paramter in the command usage for better readability. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mmc: fsl_esdhc: Add support for DDR modeVolodymyr Riazantsev2015-02-24-2/+9
| | | | | | | | | | | | | | | | Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only. Signed-off-by: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls1021x: Add support for initializing CAAM's stream idAlison Wang2015-02-24-0/+115
| | | | | | | | | | | | | | | | | | There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id for using the same SMMU3 on LS1021A. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: workaround for cache coherency problemchenhui zhao2015-02-24-0/+28
| | | | | | | | | | | | | | | | | | | | The RCPM FSM may not be reset after power-on, for example, in the cases of cold boot and wakeup from deep sleep. It causes cache coherency problem and may block deep sleep. Therefore, reset them if they are not be reset. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/pci: add Layerscape PCIe driverMinghuan Lian2015-02-24-5/+466
| | | | | | | | | | | | | | | | The patch adds Freescale Layerscape PCIe driver and provides up to 4 controllers support. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/ls1021a: add PCIe settingsMinghuan Lian2015-02-24-0/+48
| | | | | | | | | | | | | | | | The patch enables and adds PCIe settings for boards LS1021AQDS and LS1021ATWR. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/ls102xa: use a array to define pexmscportsrMinghuan Lian2015-02-24-2/+1
| | | | | | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/ls102xa: create TLB to map PCIe regionMinghuan Lian2015-02-24-10/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins 0x48_00000000. In order to access PCIe device, we must create TLB to map the 40bit physical address to 32bit virtual address. This patch will enable MMU after DDR is available and creates MMU table in DRAM to map all 4G space; then, re-use the reserved space to map PCIe region. The following the mapping layout. VA mapping: ------- <---- 0GB | | | | |-------| <---- 0x24000000 |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 |-------| <---- 0x300000000 | | |-------| <---- 0x34000000 |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 |-------| <---- 0x40000000 | | |-------| <---- 0x80000000 DDR0 space start |\\\\\\\| |\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space |\\\\\\\| ------- <---- 4GB DDR0 space end Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: Define default values for some CCSR macrosAlison Wang2015-02-24-0/+37
| | | | | | | | | | | | | | | | This patch is to define default values for some CCSR macros to make header files cleaner. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/mc: Migrated MC Flibs to 0.5.2J. German Rivera2015-02-24-52/+592
| | | | | | | | | | | | | | | | | | | | | | Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree from "fsl,dprcr" to "fsl-mc". Print MC version info when appropriate. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a_emu: Enable sync of refreshYork Sun2015-02-24-0/+1
| | | | | | | | | | | | | | Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers stay in sync. DP-DDR has only one controller so it does no harm. Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Enable erratum workround for A008514York Sun2015-02-24-0/+1
| | | | | | | | | | | | Erratum A008514 appleis to ls2085a. Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Enable workaround for A008336York Sun2015-02-24-0/+4
| | | | | | | | | | | | Erratum A008336 applied to LS2085A. Signed-off-by: York Sun <yorksun@freescale.com>
| * ls2085/configs: Ensure right banners are printed for EMU and SIMUBhupesh Sharma2015-02-24-3/+6
| | | | | | | | | | | | | | | | This patch enusres that right banners are printed for LS2085A emulator and simulator platforms. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ARMv8/ls2085a: Move kernel image load addressStuart Yoder2015-02-24-1/+1
| | | | | | | | | | | | | | | | Move the load address of the kernel image to get it away from the region of the uncompressed kernel. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ARMv8/ls2085a: Switch to passing earlycon to kernelArnab Basu2015-02-24-4/+4
| | | | | | | | | | | | | | | | Since Linux v3.16-rc1 earlyprintk has been removed for arm64. Switch to using earlycon. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Add sync of refreshYork Sun2015-02-24-0/+64
| | | | | | | | | | | | | | Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun <yorksun@freescale.com>
| * ARMv8/LS2085A: Adjust system clock and DDR clockYork Sun2015-02-24-1/+2
| | | | | | | | | | | | Set system clock to 100MHz and DDR clock to 133MHz. Signed-off-by: York Sun <yorksun@freescale.com>
| * ARMv8/LS2085A: HugeTLB support is required by default in LS NADKKuldip Giroh2015-02-24-1/+3
| | | | | | | | | | | | | | | | | | | | LS NADK memory manager by default works on HugeTLB. Hence bootargs must include parameters default_hugepagesz (default hugepagesize, hugepagesz (hugepage size) and hugepages (number of hugepages to be reserved in kernel for the given size). Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Fix a typo in timing_cfg_8 calculationYork Sun2015-02-24-1/+1
| | | | | | | | | | | | wwt_bg should match rrt_bg. It was a typo in driver. Signed-off-by: York Sun <yorksun@freescale.com>
| * ARMv8/LS2085A: Enable auto precharge for DP-DDRYork Sun2015-02-24-0/+1
| | | | | | | | | | | | | | DP-DDR benefits from auto precharge because of its specific application. Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Add support for multiple DDR clocksYork Sun2015-02-24-159/+190
| | | | | | | | | | | | | | | | | | Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Add support for second DDR clockYork Sun2015-02-24-2/+21
| | | | | | | | | | | | | | | | FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for general DDR controlers, and another clock for DP-DDR. DDR driver needs to change to support multiple clocks. Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Add workround for erratumn A008514York Sun2015-02-24-5/+17
| | | | | | | | | | | | | | Erratum A008514 workround requires writing register eddrtqcr1 with value 0x63b20002. Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Add workaround for A008336York Sun2015-02-24-0/+27
| | | | | | | | | | | | | | Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space for 64-bit DDR controllers. Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Adjust CAS to preamble override for emulatorYork Sun2015-02-24-1/+5
| | | | | | | | | | | | | | | | | | On ZeBu emulator, CAS to preamble overrides need to be set to satisfy the timing. This only impact platforms with CONFIG_EMU. These should be set before MEM_EN is set. Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Add fdt-fixup for clock frequency of the DUART nodesBhupesh Sharma2015-02-24-0/+5
| | | | | | | | | | | | | | | | This patch adds the fdt-fixup logic for the clock frequency of the NS16550A related device tree nodes. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Enable cluster timebase for all clustersYork Sun2015-02-24-2/+9
| | | | | | | | | | | | | | LS2085A and its variants can have up to four clusters. It is safe to enable timebase for all even some may be disabled. Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stackYork Sun2015-02-24-61/+97
| | | | | | | | | | | | | | | | | | | | | | | | Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com>
| * ARMv8/fsl-lsch3: Patch cpu node properties in DT for online coresArnab Basu2015-02-24-9/+23
| | | | | | | | | | | | | | | | U-Boot should only add "enable-method" and "cpu-release-address" properties to the "cpu" node of the online cores. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Change normal memory shareabilityYork Sun2015-02-24-4/+5
| | | | | | | | | | | | | | According to hardware implementation, a single outer shareable global coherence group is defined. Inner shareable has not bee enabled. Signed-off-by: York Sun <yorksun@freescale.com>
| * fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accessesBhupesh Sharma2015-02-24-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch ensures that the TZPC (BP147) and TZASC-400 programming happens for LS2085A SoC only when the desired config flags are enabled and ensures that the TZPC programming is done to allow Non-secure (NS) + secure (S) transactions only for DCGF registers. The TZASC component is not present on LS2085A-Rev1, so the TZASC-400 config flag is turned OFF for now. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-18 21:18:49 +0000