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* | | | | ARM: BeagleBoard-x15: Enable i2c5 clocksLokesh Vutla2015-06-15-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On AM57xx evm I2C5 is used to detect the LCD board by reading the EEPROM present on the bus. Enable i2c5 clocks to help that. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | am43xx_evm: Enable NAND bootTom Rini2015-06-15-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable booting from NAND on the am437xx-evm. Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | am335x_evm: nand: Fix boot from NANDRoger Quadros2015-06-15-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the correct partition names from with the Device Tree blob and the kernel is picked up. Also use partition name instead of number for the root filesystem in the kernel boot arguments. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | am335x_evm: am44xx_evm: dra7xx_evm: nand: Fix file-system partition nameRoger Quadros2015-06-15-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We almost always use UBIFS for user accessible NAND file systems and the UBIFS file system might contain more than one volume within the single NAND partition. The last NAND partition is therefore more appropriately named as "NAND.file-system" instead of "NAND.rootfs" The Linux kernel (as of v3.16) also uses "NAND.file-system" to name the last NAND partition. This patch makes the partition name consistent between u-boot and the kernel. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | configs: am43xx_evm: Enable NANDRoger Quadros2015-06-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM43xx EVMs have NAND so enable it. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | highbank: add custom ahci_link_up functionMark Langsdorf2015-06-15-1/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Calxeda highbank SOC needs a custom sequence to bring up SATA links, so override ahci_link_up with custom function to handle combophy setup. Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Richard Gibbs Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Andre Przywara <osp@andrep.de>
* | | | | ahci: extend data io wait to 10sMark Langsdorf2015-06-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AHCI driver currently waits 5s before timing out when sending a data command to a drive. Some drives take upwards of 8s to respond to the initial data command while they're spinning up. Increase the data io timeout to 10s so that those drives can be found on initial scsi scan. Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de>
* | | | | ahci: support LBA48 data reads for 2+TB drivesMark Langsdorf2015-06-12-11/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable full 48-bit LBA48 data reads by passing the upper word of the LBA block pointer in bytes 9 and 10 of the FIS. This allows uboot to load data from any arbitrary sector on a drive with 2 or more TB of available data connected to an AHCI controller. Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de> [trini: Make use of CONFIG_SYS_64BIT_LBA in a few places to drop warnings on platforms that don't enable that feature ] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | | | cmd_scsi: use lbaint_t for LBA values instead of u32Mark Langsdorf2015-06-12-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de>
* | | | | ARM: highbank: add reset support for Calxeda Midway machineMark Langsdorf2015-06-12-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Calxeda Midway part has A15 cores, which do not have the Highbank A9's SCU used there for resetting the chip. Add code to distinguish between the A9 and the A15 and invoke the appropriate register writes to support the newer part. Andre: rework detection of Highbank vs. Midway Rob: fix Andre's reworked detection Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de> Signed-off-by: Rob Herring <robh@kernel.org>
* | | | | ARM: highbank: add missing SCU register setup for resetRob Herring2015-06-12-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Andre: assign names to the magic values Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Andre Przywara <osp@andrep.de>
* | | | | ARM: BeagleBoard-x15: Add mux dataLokesh Vutla2015-06-12-38/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the mux data, manual and virtual mode settings for BeagleBoard-X15. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
* | | | | ARM: BeagleBoard-x15: Enable IO delay recalibration sequenceLokesh Vutla2015-06-12-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable IO delay recalibration sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7: CPSW: Remove IO delay hackLokesh Vutla2015-06-12-91/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now all manual mode configurations are done as part of IO delay recalibration sequence, remove the hack done for CPSW. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | | | ARM: DRA7-evm: Add mux dataNishanth Menon2015-06-12-27/+326
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the mux data, manual and virtual mode settings for DRA7-evm. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
* | | | | ARM: DRA7-evm: Enable IO delay recalibration sequenceLokesh Vutla2015-06-12-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling IO delay recalibration sequence for DRA7 EVM. UART and I2C are configured before IO delay recalibration sequence as these are used earlier and safe to use. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7: Add support for manual mode configurationLokesh Vutla2015-06-12-2/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "manual mode" also programmed, when predefined delay characteristics cannot be used for the interface. struct iodelay_cfg_entry is introduced for populating manual mode IO timings. For configuring manual mode, along with the normal pad configuration do the following steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux) - Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL. And pass the offset of the CFG_XXX register in iodelay_cfg_entry. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7: Add support for IO delay configurationLokesh Vutla2015-06-12-0/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA7, in addition to the regular muxing of pins, an additional hardware module called IODelay which is also expected to be configured. This "IODelay" module has it's own register space that is independent of the control module. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay recalibration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do muxing as part of IOdelay recalibration. IODELAY recalibration sequence: - Complete AVS voltage change on VDD_CORE_L - Unlock IODLAY config registers. - Perform IO delay calibration with predefined values. - Isolate all the IOs - Update the delay mechanism for each IO with new calibrated values. - Configure PAD configuration registers - De-isolate all the IOs. - Relock IODELAY config registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7: Add support for virtual mode configurationLokesh Vutla2015-06-12-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "virtual mode" also programmed. This allows for predefined delay characteristics to be used by the SoC to meet timing characterstics needed for the interface. Provide easy to use macro to do the same. For configuring virtual mode, along with normal pad configuration add the following two steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1 - DELAYMODE filed should be configured with value given in DATA Manual. CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7: Add pinctrl register definitionsLokesh Vutla2015-06-12-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adopting the pinctrl register definitions from Linux kernel to be consistent. Old definitions will be removed once all the pinctrl data is adapted to new definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7: Make do_set_mux32() genericLokesh Vutla2015-06-12-20/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | do_set_mux32() is redefined in dra7xx and beagle_x15 boards. IO delay recalibration sequence also needs this. Making it generic to avoid duplication. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | | | ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL registerLokesh Vutla2015-06-12-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When DLL_CALIB_INTERVAL is set, an extra delay is added which is not required and it consumes EMIF bandwidth. So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | | | ARM: DRA7: Update DDR IO registersLokesh Vutla2015-06-12-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update DDR IO register values. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: DRA7: Update DDR IO configurationLokesh Vutla2015-06-12-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDRIO_2 and LPDDR2CH1_1 registers are not present for DRA7. So not configuring these registers for DRA7xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: DRA7: Add is_dra72x cpu check definitionLokesh Vutla2015-06-12-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A generic is_dra72x cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: DRA72-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: DRA7-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on DRA7-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: BeagleBoard-X15: Enable HW levelingLokesh Vutla2015-06-12-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on BeagleBoard-X15. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | ARM: DRA7: DDR3: Add support for HW levelingLokesh Vutla2015-06-12-26/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA7 EMIF supports Full leveling for DDR3. Adding support for the Full leveling sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | | kconfiglib: sync with the latest in Kconfiglib projectMasahiro Yamada2015-06-12-7/+35
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit imports some updates of kconfiglib.py from https://github.com/ulfalizer/Kconfiglib - Warn about and ignore the "allnoconfig_y" Kconfig option - Statements in choices inherit menu/if deps - Add Symbol.is_allnoconfig_y() - Hint that modules are still supported despite warnings. - Add warning related to get_defconfig_filename(). - Fix typo in docs. - Allow digits in $-references to symbols. Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com> Signed-off-by: Philip Craig <philipjcraig@gmail.com> Signed-off-by: Jakub Sitnicki <jsitnicki@gmail.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | Nokia RX-51: Fix calculating return address in save_boot_paramsPali Rohár2015-06-12-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e11c6c279d823dc0d2f470c5c2e3c0a9854a640f broke calculating lr register in function save_boot_params() and caused U-Boot to crash at early boot time on Nokia N900 board. This patch fix calculating return address in lr register and make Nokia N900 board bootable again. Patch was tested in qemu and also on real N900 HW. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
* | | | Merge git://git.denx.de/u-boot-dmTom Rini2015-06-11-243/+309
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| * | | | dm: usb: tegra: Drop legacy USB codeSimon Glass2015-06-10-159/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop the code that doesn't use driver model for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | sandbox: Move CONFIG_SANDBOX_SERIAL to KconfigSimon Glass2015-06-10-3/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | Remove SPL undefine of CONFIG_OF_CONTROLSimon Glass2015-06-10-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow SPL to be built with this option so that we can support device tree control. Disable the simple bus for now in SPL. It may be needed later. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | Add a simple version of memalign()Simon Glass2015-06-10-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is used when the full malloc() is not available. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | dm: serial: Don't support CONFIG_CONS_INDEX with device treeSimon Glass2015-06-10-32/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature should be deprecated for new boards, and significantly adds to SPL code size. Drop it. Instead, we can use stdout-path in the /chosen node. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | dts: Disable device tree for SPL on all boardsSimon Glass2015-06-10-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We plan to enable device tree in SPL by default. Before doing this, explicitly disable it for all boards. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | fdt: arm: Drop device tree paddingSimon Glass2015-06-10-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 4KB padding doesn't seem necessary since we don't normally adjust the control device tree file within U-Boot. Also drop the memory table space. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | dm: ns16550: Support CONFIG_SYS_NS16550_MEM32 with driver modelSimon Glass2015-06-10-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option is used by some boards, so support it with driver model. This is really ugly - we should rewrite this driver once all users are moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | lcd: Support colour lookup table on 16bpp display in BMP imagesSimon Glass2015-06-10-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For 16-bit-per-pixel displays it is useful to support 8 bit-per-pixel images to reduce image size. Add support for this when drawing BMP images. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | Remove typedefs from bmp_layout.hSimon Glass2015-06-10-31/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We try to avoid typedefs and these ones are easy enough to remove. Before changing this header in the next patch, remove the typedefs. Signed-off-by: Simon Glass <sjg@chromium.org> Suggested-by: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | | sandbox: Add an implementation for cleanup_before_linux_select()Simon Glass2015-06-10-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support this function so we can use Chrome OS verified boot with sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | arm: Allow cleanup_before_linux() without disabling cachesSimon Glass2015-06-10-18/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is used before jumping to U-Boot, but in that case we don't always want to disable caches. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
| * | | | arm: spl: Add an API to detect when U-Boot is started from SPLSimon Glass2015-06-10-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For secure boot systems it is common to have a read-only U-Boot which starts the machine and jumps to a read-write U-Boot for actual booting the OS. This allows the read-write U-Boot to be upgraded without risk of permanently bricking the machine. In the event that the read-write U-Boot is corrupted, the read-only U-Boot can detect this with a checksum and boot into a recovery flow. To support this, add a way to detect when U-Boot is run from SPL as opposed to some other method, such as booted directly (no SPL) or started from another source (e.g. a primary U-Boot). This works by putting a special value in r0. For now we rely on board-specific code to actually check the register and set a flag. At some point this could be generalised, perhaps by using a spare register and passing a flag to _main and/or board_init_f(). This commit does not implement any feature, but merely provides the API for boards to implement. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | dm: usb: Implement usb_detect_change() for driver modelSimon Glass2015-06-10-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support this function with driver model also (CONFIG_DM_USB). Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | dm: tegra: usb: Move USB to driver modelSimon Glass2015-06-10-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Somehow this change was dropped in the various merges. I noticed when I came to turn off the non-driver-model support for Tegra. We need to make this change (and deal with any problems) before going further. Change-Id: Ib9389a0d41008014eb0df0df98c27be65bc79ce6 Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
| * | | | dm: i2c: Add compatibility functions for dm_i2c_reg_read/write()Simon Glass2015-06-10-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the legacy i2c_reg_read/write() functions to the compatibility layer so that they can be used when CONFIG_DM_I2C_COMPAT is defined. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* | | | | common/cmd_bdinfo: show gd->board_typeHannes Schmelzer2015-06-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sometimes it is usefull to know if board-detection has written the correct value into gd->board_type. For this we add some output to the bdinfo command. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
* | | | | blackfin: fix undefined reference to srand and randMasahiro Yamada2015-06-11-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9ba9e85f3f1c (net: Fix NET_RANDOM_ETHADDR dependencies) accidentally dropped CONFIG_LIB_RAND defines for 14 Blackfin boards. Prior to that commit, those boards defined CONFIG_LIB_RAND, but not CONFIG_NET_RANDOM_ETHADDR. So, commit 9ba9e85f3f1c should not have touched them, but in fact it ripped CONFIG_LIB_RAND off from all the header files, which caused undefined reference to srand and rand. CONFIG_LIB_RAND=y must be revived for such boards. BTW, this commit indeed makes it better, but even with this fix, three boards (bf533-stamp, bf538f-ezkit, cm-bf548) still can not build due to region 'ram' overflowed error. This was cause by commit 6eed3786c68c (net: Move the CMD_NET config to defconfigs) because CMD_NET selects NET, and NET selects REGEX. Eventually, some boards were newly enabled with CONFIG_REGEX, increasing the memory footprint. A patch is expected to fix the build error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-10-20 13:10:37 +0000