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| * power: pmic: Add support for MAX77696 PMICFabio Estevam2015-07-26-0/+93
| | | | | | | | | | | | Add support for MAX77696 PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * thermal: Fix commentsFabio Estevam2015-07-26-12/+4
| | | | | | | | | | | | | | | | | | | | It seems that many comments were copied from the I2C uclass, so adjust the comments for the thermal class. Reported-by: Simon Glass <sjg@chromium.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Simon Glass <sjg@chromium.org>
| * imx: imximage: add new CHECK/CLR BIT commandAdrian Alonso2015-07-26-27/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Extend imximage DCD version 2 to support DCD commands CMD_WRITE_CLR_BIT 4 [address] [mask bit] means: while ((*address & ~mask) != 0); CMD_CHECK_BITS_SET 4 [address] [mask bit] means: while ((*address & mask) != mask); CMD_CHECK_BITS_CLR 4 [address] [mask bit] means: *address = *address & ~mask; * Add set_dcd_param_v2 helper function to set DCD command parameters Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * arm: mx6: tqma6: Add WRU-IV baseboard for the TQMa6 SoMStefan Roese2015-07-26-0/+437
| | | | | | | | | | | | | | | | | | This patch adds support for the "OHB System AG" baseboard with is equipped with the TQMa6S SoM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Stefano Babic <sbabic@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-07-17-1771/+2544
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| * | thermal: imx_thermal: fix busywait if IMX6 temp <0CTim Harvey2015-07-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The temperature calculation must be typecasted to keep the compiler from sign extending a negative value prior to division. This fixes an issue where if the CPU temperature is <0C it will get stuck in the busywait loop until the CPU heats up to 0C. Cc: Ye Li <b37916@freescale.com> Cc: Jason Liu <r64343@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | tools: mkimage: fix imximage header sizeAlbert ARIBAUD \(3ADEV\)2015-07-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | imximage header size is 4-byte, not 8-byte aligned. This produces .imx images that a Vybrid cannot boot on. Fix by adding a "padding" field in header. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | i2c: fix vf610 supportAlbert ARIBAUD \(3ADEV\)2015-07-10-5/+17
| | | | | | | | | | | | | | | | | | | | | Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four I2C instances available in VF610. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | net: fec_mxc: remove useless struct nbufAlbert ARIBAUD \(3ADEV\)2015-07-10-15/+5
| | | | | | | | | | | | | | | | | | | | | | | | This locally defined struct is actually only used once and as an opaque type. Remove it for clarity. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | iMX: adding parsing to hab_status commandUlises Cardenas2015-07-10-13/+245
| | | | | | | | | | | | | | | | | | | | | | | | hab_status command returns a memory dump of the hab event log. But the raw data is not human-readable. Parsing such data into readable event will help to minimize debbuging time. Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
| * | imx: mx6 add i2c4 clock support for i.MX6SXPeng Fan2015-07-10-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C4 clock support for i.MX6SX. Since we use runtime check, but not macro, we need to remove `#ifdef ..` in crm_regs.h, or gcc will fail to compile the code succesfully. Making the macros only for i.MX6SX open to other i.MX6x maybe not a good choice, but we have runtime check. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | imx: mx6 remove duplicated enable_cspi_clockPeng Fan2015-07-10-21/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable_spi_clock does the same thing with enable_cspi_clock, so remove enable_cspi_clock. Remove enable_cspi_clock prototype in header file convert cm_fx6/spl.c to use enable_spi_clk Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | imx6: standardise OCOTP and fuse config to mx6_commonPeter Robinson2015-07-10-68/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | According to README.mxc_ocotp the OCOTP is a stanard i.MX6 SoC feature so centralise the config in mx6_common.h so functionality is standard across all boards Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | thermal:imx_thermal: enter busywait cooling loop when over max CPU tempTim Harvey2015-07-10-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the check for temperature being within the min/max range and enter the busywait cooling loop whenever the CPU temperature is over the critical temp. This fixes the issue where if a board was booted at a temp greater than the CPU temperature max, it would skip the loop and never indicate or try to address the overtemp issue. Cc: Ye Li <b37916@freescale.com> Cc: Jason Liu <r64343@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-07-10-6849/+11328
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| * | | mx53loco: Use generic 'load' command instead of 'fatload'Guillaume GARDET2015-07-06-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript', 'loadimage' and 'loadfdt' for mx53loco board. This allows to use EXT partition instead of FAT, while keeping FAT compatibility. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Jason Liu <r64343@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <r64343@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-07-31-152/+631
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| * | | | powerpc/T104xRDB: Remove vbank check redundant codePriyanka Jain2015-07-31-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sw variable in checkboard function is storing vbank value which can only take 3-bit value. So check of sw value for if greater than 7 is redundant. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/t1023rdb: eMMC boot without external SD cardShengzhou Liu2015-07-31-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eMMC has no CD and WP pins, it needs to add board-specific board_mmc_getcd() and board_mmc_getwp() in SPL to support eMMC boot without external SD card inserted. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/t4240: update serdes tableShaohui Xie2015-07-31-55/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3 support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes A/B/C/D are not available, updated the serdes table accordingly with some minor fix. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/t1023rdb: add support for T1023RDB RevCShengzhou Liu2015-07-31-56/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for NOR flash and GPIO/I2C switch control on RevC. - NOR support - bank0/bank4 switch - SD/eMMC switch - board version Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAMAneesh Bansal2015-07-31-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040Aneesh Bansal2015-07-31-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for NAND for P5020 and P5040. The Secure boot target has already been added for P3041 by enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM. The targets for P5020 and P5040 are added in the same manner. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041Aneesh Bansal2015-07-31-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/T102xRDB: Enable ifc nand ecc encode and decodeJaiprakash Singh2015-07-28-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC nand ecc encode and decode mode are not correctly set in CSOR register during nand initialization.Enable ecc encode/decode in 4-bit mode Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc85xx: Correct CONFIG_USB_MAX_CONTROLLER_COUNT for p1025Nikhil Badola2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1 for p1025 as it has one USB controller Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/b4860qds: Update README for DIP switch informationRaghav Dogra2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board manual desribes ON as boolean 1 and OFF as boolean 0. Updating README with correct boolean values. Signed-off-by: Raghav Dogra <raghav@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/t1024: update fman liodn for mac1Shengzhou Liu2015-07-28-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MAC1 acts as 1G/10G dual-role MAC on T1024. We introduce macro SET_FMAN_RX_10G_TYPE2_LIODN for 10G MACs which have same Port ID and same offset of address with 1G MAC. Update it to match with the setting of fman in t1024 device tree, otherwise there is no 'fsl,liodn' in /proc/device-tree/soc@ffe000000/fman@400000/port@88000/ Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/t104x, t102x: Update CPC debug register value in PBI commandsPriyanka Jain2015-07-28-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update PBI command in pbi_cfg files to keep register bit to default reset value while configuring CPC as SRAM Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/t4rdb: fix cpld reset altbankShaohui Xie2015-07-28-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpld reset altbank should always reset to bank4 no matter what current bank is. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/p2020rdb: fix the FDT_ERR_NOTFOUND issueYing Zhang2015-07-28-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the function ft_board_setup() delete the USB2 device node, it leads to can't find the device node and hung up. In fact only P1020RDB needs to delete the USB2 node, this patch fixes this issue. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/T104xD4: Add Secure boot support for T104xD4RDB platformsgaurav rana2015-07-28-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | defconfig files are added and SFP version for these platforms is updated. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/T104xD4RDB: Add T104xD4RDB boards supportPriyanka Jain2015-07-28-16/+284
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. T1040D4RDB is re-designed T1040RDB board with following changes : - Support of DDR4 memory - Support of 0x66 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 - Support of QE-TDM Similarily T1042D4RDB is a Freescale reference board that hosts the T1040 SoC. T1042D4RDB is re-designed T1042RDB board with following changes : - Support of DDR4 memory - Support for 0x86 serdes protocol which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 - Support of DIU Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | | Merge git://git.denx.de/u-boot-x86Tom Rini2015-07-31-1/+4
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| * | | | | patman: Don't run patman when it is imported as a moduleSimon Glass2015-07-31-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 488d19c (patman: add distutils based installer) has the side effect of making patman run twice with each invocation. Fix this by checking for 'main program' invocation in patman.py. This is good practice in any case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chris Packham <judge.packham@gmail.com>
* | | | | | armv8: caches: Added routine to set non cacheable regionSiva Durga Prasad Paladugu2015-07-31-10/+55
|/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-07-29-103/+4639
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| * | | | | T210: Add support for 64-bit T210-based P2571 boardTom Warren2015-07-28-0/+617
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | P2571: dts: Add DT file for Tegra210 P2571 boardTom Warren2015-07-28-1/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on T124 Venice2. SDMMC1 is SD-card slot. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | ARM: Tegra210: Add support to common Tegra source/config filesTom Warren2015-07-28-43/+509
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Derived from Tegra124, modified as appropriate during T210 board bringup. Cleaned up debug statements to conserve string space, too. This also adds misc 64-bit changes from Thierry Reding/Stephen Warren. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: Tegra210: Add SoC code/include files for T210Tom Warren2015-07-28-0/+3275
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | Tegra: Rework KConfig options to allow 64-bit builds (T210)Tom Warren2015-07-28-11/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved Tegra config options to mach-tegra/Kconfig so that both 32-bit and 64-bit builds can co-exist for Tegra SoCs. T210 will be 64-bit only (no SPL) and will require a 32-bit AVP/BPMP loader. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | Tegra210: Fix 64-bit build warning about save_boot_params_ret()Tom Warren2015-07-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simon's 'tegra124: Implement spl_was_boot_source()' needs a prototype for save_boot_params_ret() to build cleanly for 64-bit Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | ARM: tegra: Use architected timer on ARMv8Thierry Reding2015-07-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8 requires an architected timer to be present, so it can be used instead of the Tegra US timer. This allows for better code reuse. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | ARM: tegra: Initialize timer earlierThierry Reding2015-07-28-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A subsequent patch will enable the use of the architected timer on ARMv8. Doing so implies that udelay() will be backed by this timer implementation, and hence the architected timer must be ready when udelay() is first called. The first time udelay() is used is while resetting the debug UART, which happens very early. Make sure that arch_timer_init() is called before that. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | | ARM: tegra: Disable SPL and non-cached memory on 64-bitThierry Reding2015-07-28-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in AArch64 mode so that we don't need the SPL. Non-cached memory is not implemented (yet) for 64-bit ARM. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra: Use standard cache enable for 64-bitThierry Reding2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 64-bit SoCs the I-cache isn't enabled in early code, so the default cache enable functions for 64-bit ARM can be used. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCsThierry Reding2015-07-28-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most peripherals on Tegra can do DMA only to the lower 32-bit address space, even on 64-bit SoCs. This limitation is typically overcome by the use of an IOMMU. Since the IOMMU is not entirely trivial to set up and serves no other purpose (I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to the lower 32-bit address space for RAM. This ensures that the physical addresses of buffers that are programmed into the various DMA engines are valid and don't alias to lower addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | fdt: Fix fdtdec_get_addr_size() for 64-bitThierry Reding2015-07-28-20/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | armv8/cache: Fix page table creationThierry Reding2015-07-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While generating the page tables, a running integer index is shifted by SECTION_SHIFT (29) and causes overflow for any integer bigger than 7. The page tables therefore alias to the same 8 sections and cause U-Boot to hang once the MMU is enabled. Fix this by making the index a 64-bit unsigned integer and so avoid the overflow. swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and "j" varies depending on RAM size; from 4 to 11 for a board with 4GB at physical address 2GB, as some Tegra boards have. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-10-08 16:54:29 +0000