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| * | sunxi: mmc: Enable pull-up on card-detect gpio pinHans de Goede2015-06-04-1/+3
| | | | | | | | | | | | | | | | | | | | | On some boards we need to enable the internal pull-up te reliable detect that no card is inserted. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge git://git.denx.de/u-boot-fdtTom Rini2015-06-05-0/+60
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| * | | fdt: Documentation for a few support functions aside their prototypesPaul Kocialkowski2015-06-05-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This instroduces comments that explain the purpose, parameters and return codes of a few fdt support functions, that are used to fill the fdt. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Simon Glass <sjg@chromium.org>
| * | | fdt: Pass the device serial number through devicetreePaul Kocialkowski2015-06-05-0/+34
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before device-tree, the device serial number used to be passed to the kernel using ATAGs (on ARM). This is now deprecated and all the handover to the kernel should now be done using device-tree. Thus, this passes the serial-number property to the kernel using the serial-number property of the root node, as expected by the kernel. The serial number is a string that somewhat represents the device's serial number. It might come from some form of storage (e.g. an eeprom) and be programmed at factory-time by the manufacturer or come from identification bits available in e.g. the SoC. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Simon Glass <sgj@chromium.org>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2015-06-05-93/+135
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| * | | gpio: fix typos in GPIO headerMasahiro Yamada2015-06-04-8/+8
| | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | sandbox: Compile test device tree when CONFIG_UT_DM is definedSimon Glass2015-06-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A conflict between the PMIC and unit test work means that the sandbox test device tree file is no-longer built. Fix this. Series-to: u-boot Series-cc: joe, prz Change-Id: I6616428e05713e5306f848e7dd0a645dedf0934e Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: dts: Add the real-time-clock test nodes back inSimon Glass2015-06-04-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These were lost when the PMIC series was applied. Add them back so that the tests pass again. Reported-by: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | sandbox: dts: Sort the sandbox.dts fileSimon Glass2015-06-04-52/+54
| | | | | | | | | | | | | | | | | | | | | | | | Sort this by node name for easier browsing. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: dts: Sort the test.dts file a littleSimon Glass2015-06-04-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some core test nodes near the beginning of the file which should be grouped together. But for other nodes, let's sort them. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | dm: Sort the uclass IDs after the tegra/PMIC additionSimon Glass2015-06-04-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tidy up the sort order again. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | dm: pci: Allow PCI bus numbering aliasesSimon Glass2015-06-04-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9cc36a2 'dm: core: Add a flag to control sequence numbering' changed the default uclass behaviour to not support bus numbering. This is incorrect for PCI and that commit should have enabled the flag for PCI. Enable it so that PCI buses can be found and the 'pci' command works again. Also add a test for this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | sandbox: Tidy up terminal restoreSimon Glass2015-06-04-3/+15
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | For some reason 'u-boot -D' does not restore the terminal correctly when the 'reset' command is used. Call the terminal restore function explicitly in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | | x86: minnowmax: initialize the pin-muxing from device treeGabriel Huau2015-06-04-0/+10
| | | | | | | | | | | | | | | Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: gpio: add pinctrl support from the device treeGabriel Huau2015-06-04-28/+317
| | | | | | | | | | | | | | | | | | | | | | | | | | | Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: baytrail: pci region 3 is not always mapped to end of ramAndrew Bradford2015-06-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF and additional SDRAM is mapped from 0x100000000 and up. There is a physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses. Because of this, PCI region 3 should only try to use up to the amount of SDRAM or 0x80000000, which ever is less. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: qemu: Implement PIRQ routingBin Meng2015-06-04-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | Support QEMU PIRQ routing via device tree on both i440fx and q35 platforms. With this commit, Linux booting on QEMU from U-Boot has working ATA/SATA, USB and ethernet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: coreboot: Control I/O port 0xb2 writing via device treeBin Meng2015-06-04-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes U-Boot to hang on QEMU q35 target. We introduce a config option in the device tree "u-boot,no-apm-finalize" under /config node if we don't want to do that. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: qemu: Create separate i440fx and q35 device treesBin Meng2015-06-04-6/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although the two qemu-x86 targets (i440fx and q35) share a lot in common, they still have something that cannot easily handled in one single device tree). Split to create two dedicated device tree files and make the i440fx be the default build target. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: coreboot: Fix cosmetic issuesBin Meng2015-06-04-25/+3
| | | | | | | | | | | | | | | | | | | | | Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: kconfig: Make FSP_TEMP_RAM_ADDR depend on HAVE_FSPBin Meng2015-06-04-0/+1
| | | | | | | | | | | | | | | | | | | | | FSP_TEMP_RAM_ADDR should only be visible when HAVE_FSP is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | tools: ifdtool: Do not write region while its size is negativeBin Meng2015-06-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | We should ignore those regions whose size is negative. These are typically optional and unused regions (like GbE and platform data). Change-Id: I65ad01746144604a1dc0588b617af21f2722ebbf Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: qemu: Adjust VGA initializationBin Meng2015-06-04-19/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As VGA option rom needs to run at C segment, although QEMU PAM emulation seems to only guard E/F segments, for correctness, move VGA initialization after PAM decode C/D/E/F segments. Also since we already tested QEMU targets to differentiate I440FX and Q35 platforms, change to locate the VGA device via hardcoded b.d.f instead of dynamic search for its vendor id & device id pair. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: qemu: Enable legacy IDE I/O ports decodeBin Meng2015-06-04-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix driver does sanity check to see whether legacy ports decode is turned on. To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: qemu: Turn on legacy segments decodeBin Meng2015-06-04-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | By default the legacy segments C/D/E/F do not decode to system RAM. Turn on the decode via Programmable Attribute Map (PAM) registers so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: qemu: Make host bridge (b.d.f=0.0.0) visibleBin Meng2015-06-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default weak version of pci_skip_dev() in drivers/pci/pci_common.c skips the host bridge (b.d.f = 0.0.0) which is actually the i440fx/q35 chipset for QEMU targets. Define CONFIG_PCI_CONFIG_HOST_BRIDGE to make it visible in the PCI configuration space. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: fsp_support: Correct high mem comment typoAndrew Bradford2015-06-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | High mem starts at 4 GiB. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Do sanity test on pirq table before writingBin Meng2015-06-04-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | If pirq_routing_table points to NULL, that means U-Boot fails to generate the table before in create_pirq_routing_table(), so we test it against NULL before actually writing it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: quark: Implement PIRQ routingBin Meng2015-06-04-15/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Document irq router device tree bindingsBin Meng2015-06-04-0/+50
| | | | | | | | | | | | | | | | | | | | | Describe all required properties needed by the irq router device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Refactor PIRQ routing supportBin Meng2015-06-04-300/+416
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: qemu: Add ATA/SATA supportBin Meng2015-06-04-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | Enable legacy IDE support on the pc target and AHCI support on the q35 target. Default configuration is to support the pc target. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Add CONFIG_LBA48 and remove CONFIG_ATAPI in x86-common.hBin Meng2015-06-04-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | Enable CONFIG_LBA48 to support large disks. CONFIG_ATAPI is only needed by cmd_ide.c which is not common for modern x86 targets, hence remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | cmd_ide: Eliminate build warnings in atapi_inquiry()Bin Meng2015-06-04-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Eliminate the following build warning in atapi_inquiry(): "warning: assignment from incompatible pointer type [enabled by default]" Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | pci: Do not skip legacy IDE device configurationBin Meng2015-06-04-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The legacy IDE device has a BAR4 (Bus Master Interface BAR) which needs to be configured. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | | pci: Allow debug message output in pci_auto.cBin Meng2015-06-04-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the '#undef DEBUG' in pci_auto.c so that we can enable debug message output via '-DDEBUG'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: qemu: Add graphics supportBin Meng2015-06-04-9/+35
| | | | | | | | | | | | | | | | | | | | | | | | It turns out that QEMU x86 emulated graphic card has a built-in option ROM which can be run perfectly with native mode by U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Move FRAMEBUFFER_SET_VESA_MODE etc to video KconfigBin Meng2015-06-04-144/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE are not x86-specific, so move them to drivers/video/Kconfig and make them depend on VIDEO_VESA driver. Some cosmetic fixes are applied to the Kconfig help text as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | video: Kconfig: Make VESA driver avaiable for non-x86 boardsBin Meng2015-06-04-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | There is no reason to prevent CONFIG_VIDEO_VESA driver working on non-x86 boards, so remove such limitation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Remove DECLARE_GLOBAL_DATA_PTR in board filesBin Meng2015-06-04-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | gd is not referenced in those board files so DECLARE_GLOBAL_DATA_PTR should be removed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Update README.x86 for QEMU supportBin Meng2015-06-04-17/+48
| | | | | | | | | | | | | | | | | | | | | Document how to build and test U-Boot with QEMU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Change coreboot default build configuration to QEMUBin Meng2015-06-04-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | QEMU is much easier for us test booting U-Boot as a coreboot payload than having a real board like chromebook_link. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | x86: Set CONFIG_NR_DRAM_BANKS to 8 and move it to x86-common.hBin Meng2015-06-04-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some x86 boards set CONFIG_NR_DRAM_BANKS to 1, which causes incorrect DRAM size printed when booting from coreboot, like this: CPU: x86, vendor Intel, device 663h DRAM: 636 KiB Using default environment Change it to 8 which should be enough for both coreboot and bare cases, and move it to x86-common.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Make QEMU the default vendorBin Meng2015-06-04-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have QEMU support, make it the default vendor in the 'make menuconfig' screen. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | x86: Support QEMU x86 targetsBin Meng2015-06-04-1/+407
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces the initial U-Boot support for QEMU x86 targets. U-Boot can boot from coreboot as a payload, or directly without coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig https://patchwork.ozlabs.org/patch/479745/
* | | pci: Move pci_hose_phys_to_bus() to pci_common.cBin Meng2015-06-04-70/+66
|/ / | | | | | | | | | | | | | | pci_hose_phys_to_bus() is needed by several drivers. Move it to pci_common.c to avoid a broken build when CONFIG_DM_PCI is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | board/BuR/common: fix netconsoleHannes Schmelzer2015-06-02-11/+7
| | | | | | | | | | | | | | | | | | | | netconsole had become defective over time and cleanups. Because the feature is used very rarely nobody did take notice about this defect. With this patch the resulting syntax error on call will be fixed. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
* | configs: remove CONFIG_NET_MULTILars Poeschel2015-06-02-49/+0
| | | | | | | | | | | | | | | | | | CONFIG_NET_MULTI is not used anywhere and thus can safely be removed from the configs. Acked-by: Marek Vasut <marex@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
* | ARM: phytec: pcm051: Remove unneeded CONFIG_USE_IRQLars Poeschel2015-06-02-3/+0
| | | | | | | | | | | | | | | | The config for pcm051 still undef'd CONFIG_USE_IRQ. This is not needed any more since it is not defined in the whole include path before. Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-06-02-439/+1462
|\ \ | | | | | | | | | | | | | | | Fixup include/configs/unipher.h to not set CONFIG_LIB_RAND Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-05 14:40:33 +0000