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* ddr: altera: Implement universal scc_mgr_set_all_ranks()Marek Vasut2015-08-08-53/+42
| | | | | | | | Implement universal scc_mgr_set_all_ranks() function and convert various ad-hoc implementations of similar functionality to use this single function. Document the function in kerneldoc. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Shuffle around scc_mgr_set_*all_ranks()Marek Vasut2015-08-08-11/+8
| | | | | | Shuffle the code around a bit, but without any functional change. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up scc_mgr_initialize()Marek Vasut2015-08-08-4/+10
| | | | | | Clean up the comments and add kerneldoc. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Implement universal scc manager config functionMarek Vasut2015-08-08-40/+29
| | | | | | | Implement unified scc_mgr_set() function and convert all those 9 scc_mgr_set_*() ad-hoc functions to call this one function. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Reorder scc manager functionsMarek Vasut2015-08-08-100/+95
| | | | | | | This patch just puts functions which look similar next to each other, so they can be sorted out. No functional change. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up scc manager function argsMarek Vasut2015-08-08-17/+13
| | | | | | | Clean up the unused args of the functions used to configure the SCC manager. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up reg_file_set*()Marek Vasut2015-08-08-36/+7
| | | | | | | Turn the insides of these functions into trivial clrsetbits_le32() and fix the data type of their argument to reflect it's actual size. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up initialize_hps_phy()Marek Vasut2015-08-08-0/+5
| | | | | | Add brief kerneldoc. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up initialize_reg_file()Marek Vasut2015-08-08-0/+5
| | | | | | Add brief kerneldoc. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up hc_initialize_rom_data()Marek Vasut2015-08-08-10/+10
| | | | | | Clean the function up, fix data types, add kerneldoc. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Massage addr into I/O accessorsMarek Vasut2015-08-08-424/+248
| | | | | | | | Get rid of invocations of this sort: addr = (u32)&base->reg; writel(val, addr); Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directlyMarek Vasut2015-08-08-15/+9
| | | | | | | Use the proper structure which describes these registers, especially since this is already in place. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESSMarek Vasut2015-08-08-236/+236
| | | | | | | Just trim down the constant SOCFPGA_SDR_ADDRESS + SDR_PHYGRP.*ADDRESS in the code. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Pluck out remaining sdr_get_addr() callsMarek Vasut2015-08-08-119/+75
| | | | | | | Remove the remaining invocations of sdr_get_addr() and the function itself. This makes the code a bit less cryptic. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*)Marek Vasut2015-08-08-26/+26
| | | | | | | Instead of this indirection, just adjust the register pointer and directly use the register base address. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*)Marek Vasut2015-08-08-63/+63
| | | | | | | Instead of this indirection, just adjust the register pointer and directly use the register base address. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*)Marek Vasut2015-08-08-45/+45
| | | | | | | Instead of this indirection, just adjust the register pointer and directly use the register base address. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*)Marek Vasut2015-08-08-22/+24
| | | | | | | Instead of this indirection, just adjust the register pointer and directly use the register base address. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)"Marek Vasut2015-08-08-3/+3
| | | | | | | Instead of this indirection, just adjust the register pointer and directly use the register base address. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Clean up ugly casts in sdram_calibration_full()Marek Vasut2015-08-08-29/+21
| | | | | | | Use the correct formating string in those debug_cond() invocations and zap those unnecessary ugly casts. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Minor indent fix in set_rank_and_odt_mask()Marek Vasut2015-08-08-1/+1
| | | | | | | Fix the position of the } else { statement to make it correctly indented. Signed-off-by: Marek Vasut <marex@denx.de>
* Makefile: Add target for building bootable SPL image for SoCFPGAMarek Vasut2015-08-08-0/+22
| | | | | | | | | | | | Add build target for generating boot partition images recognised by the SoCFPGA BootROM. The SoCFPGA BootROM expects four copies of the u-boot-spl-dtb.sfp at the beginning of boot partition. Those are u-boot-spl-dtb.bin augmented by a header with which the BootROM can work. The u-boot-dtb.img uImage is appended to this to produce a full boot partition image, the u-boot-with-spl-dtb.sfp . This is the name of the final target. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD usefulMarek Vasut2015-08-08-0/+4
| | | | | | | | Enable the mtdparts command and related options to make support for SPI NOR MTD useful in any way. With the mtdparts command in place, it is possible to use partition of the SPI NOR in U-Boot. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: config: Fix LOADADDRMarek Vasut2015-08-08-2/+2
| | | | | | | | | Setting LOADADDR to 0x8000 is a bad idea, it is very likely that some kind of overlap will happen. Move the LOADADDR 0x01000000 (16MiB from start of RAM) to make sure no overlap happens when loading kernel for example. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: config: Enable CONFIG_SPI_FLASH_BARMarek Vasut2015-08-08-0/+1
| | | | | | | This is needed to access broken (read: Micron) SPI flashes which are larger than 16 MiB and don't correctly support 4-byte addressing. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL buildMarek Vasut2015-08-08-0/+2
| | | | | | | We do not need full MTD support in the SPL build, it only adds size and is not usable in any way. Exclude it. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: config: Zap incorrect config optionsMarek Vasut2015-08-08-7/+2
| | | | | | | | | | | | | | There is no need to disable support for partitions in the SPL, we can support partitions in SPL perfectly well. This is likely some remnant from old times, so just remove this configuration option. Moreover, the CRC32 chunk size doesn't have to be adjusted anymore, since both the GD and malloc area are in RAM by the time this CRC check can be used and there's plenty of space. Zap this abomination as well. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: config: Move SPL GD and malloc to RAMMarek Vasut2015-08-08-6/+20
| | | | | | | | | | | Now that the SPL structure is organised such that it matches the U-Boot's SPL design, it is possible to use the option of relocating GD to RAM. And since we have GD in RAM, move malloc area to RAM as well. We point the malloc base pointer 1 MiB past U-Boot's load address. We use simple malloc for SPL because it is 3kiB smaller in terms of code size than regular malloc which was used thus far. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: misc: Reset ethernet from OFMarek Vasut2015-08-08-21/+51
| | | | | | | | | | | Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc hardcoded values in the U-Boot code. Since we don't have a proper reset framework in place yet, we have to do this slightly ad-hoc parsing of the OF tree instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* arm: socfpga: misc: Probe ethernet GMAC from OFMarek Vasut2015-08-08-5/+3
| | | | | | | | | The GMAC can now be probed from OF, so enable DM ethernet and remove the old ad-hoc designware_initialize() invocation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* arm: socfpga: misc: Export bootmode into environment variableMarek Vasut2015-08-08-11/+24
| | | | | | | | setenv an environment variable called "bootmode" , which contains the board boot mode. This can be in turn used in scripts to determine from where to load kernel and such. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: misc: Add support for printing boot modeMarek Vasut2015-08-08-0/+13
| | | | | | | Add support for printing from which device the SoCFPGA board booted. This decodes the BSEL settings and prints it in human readable form. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: misc: Fix warm resetMarek Vasut2015-08-08-0/+10
| | | | | | | | | | | | | | Write necessary magic value into the Warm Boot from ON-Chip RAM group Enable register to enable Warm reset support. Instead of doing this in the reset_cpu() function, we do it in arch early init to avoid breaking old kernel code which expects this magic value to be already written into this register. This magic is originally excavated from common/spl/spl.c in the u-boot port from altera, where this value was written just before the SPL jumped to actual U-Boot in the RAM. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add support for selecting boot device from BSELMarek Vasut2015-08-08-12/+23
| | | | | | | | Rework spl_boot_device() such that it reads the BSEL settings from system manager and decides from where to load U-Boot based on this information. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add support for booting from QSPIMarek Vasut2015-08-08-1/+28
| | | | | | | Add code and configuration options to support booting from QSPI NOR. Enable support for booting from QSPI NOR. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add support for booting from SD/MMCMarek Vasut2015-08-08-1/+37
| | | | | | | | | | Add code and configuration options to support booting from RAW SD/MMC card as well as for ext4/vfat filesystems. Enable support for booting from SD/MMC card, but don't enable the filesystem support just yet to retain compatibility with old SoCFPGA card format. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Remove custom linker scriptMarek Vasut2015-08-08-48/+0
| | | | | | | | Remove the custom SPL linker script, use the generic one instead. The custom script doesn't bring in anything new and is only burden to maintain. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Merge spl_board_init() into board_init_f()Marek Vasut2015-08-08-18/+12
| | | | | | | | | | The code in spl_board_init() should have been in board_init_f() from the beginning, since it is code which configures system and then starts DRAM. Thus, it cannot be in spl_board_init(), which is called from board_init_r() , which already expects a working DRAM. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add missing reset logicMarek Vasut2015-08-08-1/+9
| | | | | | | | Make sure that all the peripherals are correctly reset and then brought out of reset in the SPL. Not going through proper reset cycle might leave the IP blocks in inconsistent state. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Configure SCU and NIC-301 earlyMarek Vasut2015-08-08-0/+22
| | | | | | | | | Configure the ARM SCU and NIC301 very early. The ARM SCU SNSAC register must be configured, so we can access all peripherals. The NIC-301 must be configured so that the BootROM is not mapped into the SDRAM address space. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Toggle warm reset config I/O bitMarek Vasut2015-08-08-0/+5
| | | | | | | Synchronise the SPL behavior with the original Altera code and toggle the Warm Reset Config I/O bit accordingly. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: system: Clean up pinmux_config.cMarek Vasut2015-08-08-14/+43
| | | | | | | | | | | | | | | Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux table and it's size from the QTS-generated pinmux_config.c. The target here is again to get rid of poluting global namespace by including the pinmux_config.h into it. Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros, which are explicitly useless to us in U-Boot. Instead, U-Boot does use DT to detect exactly these configuration options. This patch makes sure that while this QTS-generated file can stay in the tree, these obscure macros do not ooze into the namespace anymore. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()Marek Vasut2015-08-08-5/+9
| | | | | | | | Rework sysmgr_enable_warmrstcfgio() into sysmgr_config_warmrstcfgio(), which allows both enabling and disabling the warm reset config I/O functionality. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: scan: Zap iocsr_scan_chain*_table()Marek Vasut2015-08-08-35/+54
| | | | | | | | | | | | | | | | | | | | | | Introduce accessor iocsr_get_config_table() for retrieving IOCSR config tables. This patch is again trimming down the namespace polution. The IOCSR config tables are used only by scan manager, they are generated by qts and are board specific. Before this patch, the approach to use these tables in scan manager was to define an extern variable to silence the compiler and compile board-specific iocsr_config.c into U-Boot which defined those extern variables. Furthermore, since these are tables and the scan manager needs to know the size of those tables, iocsr_config.h is included build-wide. This patch wraps all this into a single accessor which takes the scan chain ID and returns pointer to the table and it's size. All this is wrapped in wrap_iocsr_config.c board-specific file. The file includes the iocsr_config.c (!) to access the original tables and transitively iocsr_config.h . It is thus no longer necessary to include iocsr_config.h build-wide and the namespace polution is trimmed some more. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: scan: Zap redundant params in scan_mgr_io_scan_chain_prg()Marek Vasut2015-08-08-13/+26
| | | | | | | | | It is sufficient to pass in the scan chain ID into the function to determine the remaining two parameters, so drop those params and determine them locally in the function. The big-ish switch in the function is temporary and will be replaced by a proper function call in subsequent patch. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg()Marek Vasut2015-08-08-16/+9
| | | | | | | | This function is never used outside of scan_manager.c , so make it static. Zap the prototype in scan_manager.h and move the documentation above the function. Make the documentation kerneldoc compliant. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: clock: Clean up pll_config.hMarek Vasut2015-08-08-129/+169
| | | | | | | | | | | | | | | | | | | | | | | Extract the clock configuration horribleness caused by pll_config.h in the following manner. First of all, introduce a few new accessors which return values of various clocks used in clock_manager.c and use them in clock_manager.c . These accessors replace those few macros which came from pll_config.h originally. Also introduce an accessor which returns the struct cm_config default configuration for the clock manager used in SPL. The accessors are implemented in a board-specific wrap_pll_config.c file, whose sole purpose is to include the qts-generated pll_config.h and provide only the necessary values to the clock manager. The purpose of this design is to limit the scope of inclusion for the pll_config.h , which thus far was included build-wide and poluted the namespace. With this change, the inclusion is limited to just the new wrap_pll_config.c file, which in turn provides three simple functions for the clock_manager.c to use. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: clock: Get rid of cm_config_t typedefMarek Vasut2015-08-08-5/+5
| | | | | | Get rid of this cryptic typedef and replace it with explicit struct cm_config. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: reset: Add SDMMC, QSPI and DMA definesMarek Vasut2015-08-08-0/+3
| | | | | | | Add SDMMC, QSPI and DMA reset defines. These are needed by SPL so that we can boot from SD card and QSPI. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: reset: Add function to reset add peripheralsMarek Vasut2015-08-08-0/+14
| | | | | | | Add socfpga_per_reset_all() function to reset all peripherals but the L4 watchdog. This is needed in the SPL. Signed-off-by: Marek Vasut <marex@denx.de>
generated by cgit v1.1 at 2024-10-09 13:17:44 +0000