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* MLK-12495 mx6: Add LDO bypass supportYe Li2017-04-05-2/+574
| | | | | | | | | | | | | | | | Port LDO bypass support from v2015 to support the features: 1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages. LDO bypass is dependent on the flatten device tree file. 2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to reboot whole board, so split these code to independent function so that board file can call it freely. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5b87d04dba66fa45375d59648838ef89f559f75d)
* MLK-12436-17: imx: mx6sxsabreauto: update board and headerYe Li2017-04-05-26/+40
| | | | | | | | | | | | Align with imx_v2016.03 1. Update pmic settings to enable SD3 power and use PMIC common init codes. 2. Enable bmode. 3. Update MMC root parameters 4. Update AUXBOOT for M4 Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 0816a496fbe3f7d0e4f1a9322c76908a5c557c8c) Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12436-16: imx: mx6sxsabresd: update board and headerPeng Fan2017-04-05-24/+169
| | | | | | | | | | | | | | Align with imx_v2016.03. Add emmc support which needs board rework. Add I2C2. Update pmic settings. Add bmode. Move partial code from board_early_init_f to board_init. Add PCI power and reset GPIO and disable PCI at default. Update QSPI settings. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 9613a2d07760f56b3c93779b14ad32ef69856da7)
* MLK-12436-13: mx6ulevk: Add usb ethernetPeng Fan2017-04-05-0/+2
| | | | | | | | Align with imx_v2016.03. Add usb ethernet support, since there is no FEC on this i.MX6UL Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 9811e3db89f535e54ae10a10caa660f8e6036270)
* MLK-12436-12: mx6slevk: update board codePeng Fan2017-04-05-6/+101
| | | | | | | | | | | | | | Add elan code, to handle epdc which has i2c devices. In imx_v2015.04, the two pathces are for elan. b6ba68516b681a38025252bd0ef6a6ed3e8adfa0 MLK-10215 Add elan init in i.MX6SL-EVK board 0c600f6a67f00fe0c674c08c355bea3789109679 MLK-10885 imx: mx6slevk ignore elan init when no epdc on board Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit cb249aa1d57788c52145d28f2e2c68cb320d8ae3) Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12436-11: mx6sabresd: add 6qp and solo build targetPeng Fan2017-04-05-0/+122
| | | | | | | | Add default build target for mx6qp and mx6solo. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 1a2bbdea962ab4dde3838430a06be9140af5176d) Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12436-10: mx6sabresd: update board code and header fileYe Li2017-04-05-32/+166
| | | | | | | | | | | Align board code and header file with imx_v2016.03. Update pmic settings for i.MX6QP. wrap spi code together using CONFIG_MXC_SPI macro. To i.MX6SOLO, need to define nosmp in bootargs. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit bb35d09d140efc7ff9b74bbcd77d7827c1dd503e) Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12735 mx6qpsabresd: Update DDR script to version 1.14Ye Li2017-04-05-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR script file: arik_r2_sdb_ddr3_528_1.14.inc Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1 Update: setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10) setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00) setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10) setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10) setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10) setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10) setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10) setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10) setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 setmem /32 0x021b48c0 = 0x24914452 setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1 Test: Passed stress memtester on one board. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit b7f43f47a78c9d0c14fe104daf22efab13709ab1) (cherry picked from commit f521de2c5b79ab7f9b60b26cbe6a7ad50cfce9fa)
* MLK-12436-9: mx6sabresd: update ddr scriptPeng Fan2017-04-05-79/+313
| | | | | | | | | | | | | Align ddr script with imx_v2016.03 latest ddr script. mx6qp.cfg is 1.13 version http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4 http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI arik_r2_sdb_ddr3_528_1.13.inc is for sabresd Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 39c2989e6ba0de6b35b2d93acd9d67f889ab4b39)
* MLK-12436-8: imx: mx6qsabreauto: misc board updatePeng Fan2017-04-05-38/+214
| | | | | | | | | | | | | | | | To Align with imx_v2016.03. 1. Add USDHC1 support on mother board 2. Add SPINOR flash support. 3. Add enet ref clk pinmux setting and enet settings 4. Use CONFIG_SYS_USE_EIMNOR to wrap eimnor settings. 5. update mmc board settings 6. update board_init and move nand settings to board_init, but not in board_early_init_f 7. update pmic settings to align with datasheet. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit f05f2281548ab7b47f69b2c517eb6f85ad09a5d2) Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12436-7: imx: mx6qsabreauto: add solo board supportPeng Fan2017-04-05-0/+163
| | | | | | | | Add solo version ddr script and build target. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 54af2f744c663ac2326c1488a26fac0c4ccdad09) Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14261-2 mx6solo: Add nosmp kernel bootargsYe Li2017-04-05-2/+9
| | | | | | | For i.MX6 SOLO sabreauto and sabresd boards, add the "nosmp" kernel bootargs. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14261-1 mx6solo: Rename the CONFIG_MX6SOLO to CONFIG_MX6SYe Li2017-04-05-4/+8
| | | | | | | | | | | | | Since there is already CONFIG_MX6S used for i.MX6 SOLO in u-boot codes, we don't need to add new CONFIG_MX6SOLO. Rename the existing CONFIG_MX6SOLO to CONFIG_MX6S. Additional, for CONFIG_MX6S, we should select CONFIG_MX6DL. The major difference for these two chips are core number and DDR controller. So all duallite relevant definitions can apply to solo. User can combine the two configs if any code only apply to solo or duallite. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12436-6: imx: mx6dqpsabreauto: update ddr script to 1.13Peng Fan2017-04-05-5/+6
| | | | | | | | | | | | | | | | | | | | DDR script: http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4 http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI Patch in imx_v2015.04: " commit 5fb08a4dcc7b8478fc4236b90ad8dc2190cf94e7 Author: Peng Fan <Peng.Fan@freescale.com> Date: Wed Nov 4 16:30:47 2015 +0800 "MLK-11825 imx: mx6dqp: update ddr script to 1.13" " Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit d756891b9d303e456f59a18d5fa81969a7f37337) Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12436-4: mx6qarm2: update board headerPeng Fan2017-04-05-2/+4
| | | | | | | | | Define CONFIG_MMCROOT, CONFIG_SYS_MMC_ENV_PART to align with imx_v2016.03. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit b06ddb7a09346bf21028a239e77d5bf92469a284) Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12436-3: mx6qarm2: add new board revision supportPeng Fan2017-04-05-0/+320
| | | | | | | | | | | | | | | | Add mx6qarm2 new board revision support using mx6q pop SoC Enable DRAM support for imx6q PoP SoC with populated LPDDR2 MT42L128M64D2 DDR calibration script: http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/040ee38ba9ad238fcb6053b663746d51321abb69 Test result: Stress test passed. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> (cherry picked from commit b0ac10892cad46c22accf89c04ea59c46bd9eb01)
* MLK-12436-2: mx6qarm2: update ddr scriptsPeng Fan2017-04-05-1/+176
| | | | | | | | | | | | | | | | | | | | | | | | ALign with imx_v2015.04. Also to lpddr2 support: From commit: "620cf5f3d4cf37b065b5857a8ea91d61bf6c471d" " Current uboot supports for running LPDDR2 at 400MHz on MX6Q ARM2 board, but there is a problem in switching pre_periph_clk_sel to pll2_pfd2. We cannot directly change the parent of pre_periph_clk_sel as this mux is not a glitchless mux. We need to follow the correct procedure and wait for the busy bits to clear before switching. Change to follow the procedure: 1. Set periph_clk2 to OSC. 2. Switch the periph_clk to periph_clk2, checking the CCM_CDHIPR for periph_clk , ahb_podf and axi_podf busy bits. 3. Setting the pre_periph_clk to PLL2 PFD 396M. 4. Switch the periph_clk back to pre_periph_clk and checking CCM_CDHIPR busy bits. " Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> (cherry picked from commit febf98c68853030ce5c1f9124e77d75456e71314)
* MLK-12436-1: mx6qarm2: support i.MX6DQ PoP lpddr2 boardPeng Fan2017-04-05-2/+36
| | | | | | | Add the support for i.MX6DQ PoP lpddr2 ARM2 board. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit e8777e91a239599ffd231ef56c60d49b68e5e3fc)
* MLK-14250-6 mx6dq/dl: Add plugin boot support for arm2 boardsYe Li2017-04-05-2/+1304
| | | | | | | | | | | | | Add plugin.S for plugin boot initialization on mx6dq/dl arm2 board. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. New build configurations are added for the plugin: mx6dlarm2_lpddr2_plugin_defconfig mx6dlarm2_plugin_defconfig mx6qarm2_lpddr2_plugin_defconfig configs/mx6qarm2_plugin_defconfig Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14250-5 mx6ulevk: Add plugin boot supportYe Li2017-04-05-0/+446
| | | | | | | | | | Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. Add build configurations for the plugin: mx6ul_14x14_evk_plugin_defconfig mx6ul_9x9_evk_plugin_defconfig Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14250-4 mx6dq/dl/dqp: Add plugin boot support for sabre boardsYe Li2017-04-05-5/+1640
| | | | | | | | Add plugin.S for plugin boot initialization on mx6dq/dl/dqp sabresd and sabreauto boards. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. Add the configurations for the plugin enabled buiding. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14250-3 mx6sxsabreauto: Add plugin boot supportYe Li2017-04-05-1/+199
| | | | | | | | Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. Add the build configuration "mx6sxsabreauto_plugin_defconfig" to use the plugin. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14250-2 mx6sxsabresd: Add plugin boot supportYe Li2017-04-05-1/+176
| | | | | | | | Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. Add the build configuration "mx6sxsabresd_plugin_defconfig" to use the plugin. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14250-1 mx6slevk: Add plugin boot supportYe Li2017-04-05-1/+232
| | | | | | | | Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. Add the build configuration "mx6slevk_plugin_defconfig" to use the plugin. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2017-04-05-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2) (cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82) (cherry picked from commit d85cd484e6825631aa1ab572e5e0539f2191d795) (cherry picked from commit 2b29c1873c2293abe1c4b361392521223b9c9ecf)
* MLK-13782 net: fec_mxc: specify the registered eth index by dev_idAndy Duan2017-04-05-2/+9
| | | | | | | Specify the registered eth index by dev_id. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit df42b7b0c5e6847f32419075eb25f274ed039d6f)
* MLK-13777 net: fec_mxc: avoid transfer dev_id -1 to get mac address from fuseAndy Duan2017-04-05-2/+2
| | | | | | | | Avoid transfer parameter dev_id value with "-1" to .fec_get_hwaddr(), it should transfer fec->dev_id to get mac address from fuse. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit 7e4a55b068311d46d16e86e697d36f34a59bf47a)
* MLK-13486: imx: logos: use NXP logoPeng Fan2017-04-05-0/+0
| | | | | | | | | Use NXP logo. The vendor and board dir not changed, only replace the contents of freescale.bmp. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 0b381fdf1a45cb06a057724e708ce0bbeee67f4d)
* MLK-13410 Android: Change to set mfgtool only for none android u-bootYe Li2017-04-05-2/+2
| | | | | | | | | | | The mfgtool environments only can set in BSP u-boot image, not for android u-boot. Since android u-boot may go into fastboot in board_r phase which is earlier than mfgtool environment check. The USB status from android fastboot will cause u-boot to configure mfgtool environment. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 066f001a19bdc51b0fc0d65bcb87081b01f957c2) (cherry picked from commit 03f995630f92462081e98412a0fbc86bb5106f10)
* MLK-13307-12 imx: mx6: update ccm macro settings for i.MX6SLLPeng Fan2017-04-05-10/+52
| | | | | | | | Update CCM macros for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> (cherry picked from commit f735f8ac328aa49759f6db524f7c2ba32622f711)
* MLK-13307-7 imx: mx6sll: update soc settingsPeng Fan2017-04-05-2/+11
| | | | | | | Update soc settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit afa2d78f2b799337eae3dc67c0ed702d5520eee6)
* MLK-12883 usb: limit USB_MAX_XFER_BLK to 256Peng Fan2017-04-05-1/+3
| | | | | | | | | | | | | | | | | | | | For Some USB mass storage devices, such as: " - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA - Class: (from Interface) Mass Storage - PacketSize: 64 Configurations: 1 - Vendor: 0x0930 Product 0x6545 Version 1.16 " When `usb read 0x80000000 0 0x2000`, we met "EHCI timed out on TD - token=0x80008d80". The devices does not support scsi VPD page, we are not able to get the maximum transfer length for READ(10)/WRITE(10). So we limit this to 256 blocks as READ(6). Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit df0052575b2bc9d66ae73584768e1a457ed5d914)
* MLK-12444-2 mx6: Modify kernel and fdt load address to align with mfgtoolYe Li2017-04-05-4/+5
| | | | | | | | | Change the CONFIG_LOADADDR to 0x80800000 and environment variable "fdt_addr" to 0x83000000 for i.MX6SX, i.MX6SL and i.MX6UL to align the address used in mfgtool. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 41a6f612f6ae638ac6db61c60e19dcfebf052820)
* MLK-12444-1 mfgtool: Add mfgtool supportYe Li2017-04-05-1/+137
| | | | | | | | | | | | | If boot from usb, reset environment to default value. Auto apply mfgtools setting and boot mfgtools kernel. Porting this from fsl uboot to uboot 2016. The 7dsabresd has already added the environment and usb boot related functions. No need to add them more. Only need to add NAND parts environment for mfgtools. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit a352ed3c5184b95c4c9f7468f5fbb5f43de5e412)
* MLK-14259-3 mx6ulevk: Add support for NANDYe Li2017-04-05-2/+77
| | | | | | | Add NAND pinmux settings, clock setting and related configurations. Default not enabled, need hardware rework. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14259-2 mx6ulevk: Add PHYS_SDRAM_SIZE and CMA macroYe Li2017-04-05-0/+10
| | | | | | | | Define PHYS_SDRAM_SIZE future usage. Define CMA for kernel usage, default is 320MB, but we do not have enough memory on 9x9 evk lpddr2 board, so swith to 96MB. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-14259-1 mx6ulevk: Change i.MX6UL EVK to non-SPL at defaultYe Li2017-04-05-22/+362
| | | | | | | Current i.MX6UL EVK boards enable the SPL u-boot. Change it to non-SPL for default configurations. Add two other build configurations for SPL. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12767 imx6ull: fix runtime checking for i.MX6ULLPeng Fan2017-04-05-3/+3
| | | | | | | | Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL) to avoid using wrong code path. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 05922b0abf848949df778c19312cb1cf7fdfbe6a)
* MLK-12766 net: fec: do not access reserved register for i.MX6ULLPeng Fan2017-04-05-1/+1
| | | | | | | | | | The MIB RAM and FIFO receive start register does not exist on i.MX6ULL. Accessing these register will cause enet not work well or cause system report fault. Reported-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 5fb09cab9bb3cc4cef02239299d02cec666396ab)
* MLK-12565 mx7: rdc: Change IS_ENABLED to remove build warningYe Li2017-04-05-2/+3
| | | | | | | | Change to use #ifdef not the IS_ENABLED, because we will get build warning when the CONFIG_IMX_RDC is not set. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit a212eff242efb8dc171479cbaca34049d508f87b)
* MLK-10708 imx:mx6qp Update Saturation THR for PRExPeng Fan2017-04-05-4/+4
| | | | | | | | | | Update settings for PRE. Value for Saturation THR of PREx, changed from 0x20 to 0x10 to make system more stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 02e7090604e55d9690532294b02b499609d46e63) (cherry picked from commit f7c5cf580fcc2c8ab95a8d835f5874d26216910f) (cherry picked from commit 1a90b60731cd60feba1ef7a11ede2613283bb4a8)
* MLK-12483-5 mx6ul: Enable module fuse check EVK boardYe Li2017-04-05-1/+24
| | | | | | | | Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for module fuse check. And modify board level codes for SD, FEC and EIM. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 9232e9f7637afa3b71b43ab2d1361582ec5a080a)
* MLK-12483-4 mx6: Modify drivers to disable fused modulesYe Li2017-04-05-10/+136
| | | | | | | | | | | Add the fuse checking in drivers, when the module is disabled in fuse, the driver will not work. Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C, USB-EHCI, GIS, LCDIF. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
* MLK-12483-3 mx6: Add a module fuse checkingYe Li2017-04-05-1/+401
| | | | | | | | | | | | | | | | Implement a functionality to read the soc fuses and check if any module is fused. For fused module, we have to disable it in u-boot dynamically, and change the its node in FDT to "disabled" status before starting the kernel. In this patch, we implement the ft_system_setup for FDT fixup. This function will be called during boot process or by "fdt systemsetup" command. To enable the module fuse checking, two configurations must be defined: CONFIG_MODULE_FUSE CONFIG_OF_SYSTEM_SETUP Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 7236051526b73a5a25cc8330a79f5c08b7d70726)
* ENGR00315894-55 iMX6SX: add debug monitor supportYe.Li2017-04-05-0/+22
| | | | | | | | | | | | | | Debug monitor will print out last failed AXI access info when system reboot is caused by AXI access failure, only works when debug monitor is enabled. Enable this module on i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit df6ac8531d498021ed379c74fc1847bd2cec7179) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 4f4ecdbf6fe2673b8ad117df1a4974bdb7e6aa4a)
* MLK-10674-2 imx: mx6qp settings for PREPeng Fan2017-04-05-2/+31
| | | | | | | | | | | | | | | | | | | | | | | Since the following piece settings can not be in DCD table, we add them in enable_ipu_clock. " setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0 setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1 setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2 setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3 setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0 setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1 setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2 setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE " CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h, the settings sure will effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71) (cherry picked from commit 3d25e2acd48f605678a98cf594a715809dea8286)
* MLK-10496: Check the PL310 version for applying errataNitin Garg2017-04-05-9/+18
| | | | | | | | | | | | Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 31751fa9cf29ef4056f49fe06a54700a89c9bdc5)
* MLK-10176-6 imx: mx7: Modify GPT timer driver for mx7Peng Fan2017-04-05-2/+8
| | | | | | | | | | | | | Modify the GPT common platform driver for mx7 which only use 24Mhz OSC as clock source. Note: at default, the mx7d will use system counter as timer. The GPT is disabled. Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 6e250796d6a07d84093eeae96e5a6e4c593cdb0b) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 708898fe547bd3d56f0abf7e40f1af91cf4271cf)
* ENGR00328312 i2c: imx: Optimize the i2c device recovery solutionFugang Duan2017-04-05-2/+26
| | | | | | | | | | | | | | | | | | | From i2c spec, if device pull down the SDA line that causes i2c bus dead, host can send out 9 clock to let device release SDA. But for some special device like pfuze100, it pull down SDA line and the solution cannot take effort. The patch just add NACK and STOP signal after 8 dummy clock, and pmic can release SDA line after the recovery. Test case catch 375 times of i2c hang, and all are recovered. Signed-off-by: Fugang Duan <B38611@freescale.com> (cherry picked from commit 53118db42d201d36ca9067b4bb0e2702399e100b) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit b8dcb812401026cb2189b24a4f6058830151c85a) (cherry picked from commit c5a44a2a0b2218221cb12645b10f0b34ecc6f79b)
* MLK-10576 ARM: i.MX6: exclude the ARM errata from i.MX6 UP systemNitin Garg2017-04-05-5/+9
| | | | | | | | | | | | | | | | | The ARM errata 751472, 794072, 761320, 845369 only applied to the following configuration: This erratum affects configurations with either: - One processor if the ACP is present - Two or more processors i.MX6 family does not have the ACP and thus only the MPCore system will be impacted, which are the i.MX6DQ, i.MX6DL, and i.MX6QP. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> (cherry picked from commit 0db960784ba4f631ee5c0321b5d25f3b1ac55640) (cherry picked from commit 850f27d137a083a141c99fe9828d596807937d38)
generated by cgit v1.1 at 2024-11-19 10:27:12 +0000