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* cgtqmx6eval: Add thermal supportOtavio Salvador2015-07-26-0/+11
| | | | | | | | Add thermal support so that we can see the following message on boot: CPU: Industrial temperature grade (-40C to 105C) at 33C Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add ESDHC3 supportOtavio Salvador2015-07-26-1/+21
| | | | | | | | cgtqmx6eval has an eMMC connected to ESDHC3. Add support for it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Fit into single linesOtavio Salvador2015-07-26-4/+2
| | | | | | There is no need to use multiple lines when they fit into a single line. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Improve the error handlingOtavio Salvador2015-07-26-3/+7
| | | | | | | | Perfoming an OR operation on the error is not a good approach. Return the error immediately for each ESDHC instance instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Staticize when possibleOtavio Salvador2015-07-26-4/+4
| | | | | | Declare 'static' when possible. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Use the default CONFIG_SYS_PBSIZEOtavio Salvador2015-07-26-3/+0
| | | | | | | | | | | | | Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the extra characters of the error message: "Unknown command '' - try 'help'". Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve this problem. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Use default promptOtavio Salvador2015-07-26-3/+0
| | | | | | Remove the custom prompt and use the default instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mmc:fsl_esdhc invalidate dcache before readPeng Fan2015-07-26-0/+8
| | | | | | | | | | | | | | | | | | | | | DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on. We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again. With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* mx6sxsabresd: Use 'int' for return valuesFabio Estevam2015-07-26-1/+2
| | | | | | | | | | The variable 'ret' is used to store the value returned by pfuze_mode_init(), so it should be of type 'int' instead of 'unsigned int' in order to correctly handle negative numbers. Fix the variable type. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6sabresd: Use 'int' for return valuesFabio Estevam2015-07-26-1/+2
| | | | | | | | | | The variable 'ret' is used to store the value returned by pfuze_mode_init(), so it should of type 'int' instead of 'unsigned int' in order to correctly handle negative numbers. Fix the variable type. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* warp: Add MAX77696 supportFabio Estevam2015-07-26-0/+61
| | | | | | | | Warp has a MAX77696 PMIC connected via I2C1 bus. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* power: pmic: Add support for MAX77696 PMICFabio Estevam2015-07-26-0/+93
| | | | | | Add support for MAX77696 PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* thermal: Fix commentsFabio Estevam2015-07-26-12/+4
| | | | | | | | | | It seems that many comments were copied from the I2C uclass, so adjust the comments for the thermal class. Reported-by: Simon Glass <sjg@chromium.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Simon Glass <sjg@chromium.org>
* imx: imximage: add new CHECK/CLR BIT commandAdrian Alonso2015-07-26-27/+93
| | | | | | | | | | | | | | | * Extend imximage DCD version 2 to support DCD commands CMD_WRITE_CLR_BIT 4 [address] [mask bit] means: while ((*address & ~mask) != 0); CMD_CHECK_BITS_SET 4 [address] [mask bit] means: while ((*address & mask) != mask); CMD_CHECK_BITS_CLR 4 [address] [mask bit] means: *address = *address & ~mask; * Add set_dcd_param_v2 helper function to set DCD command parameters Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* arm: mx6: tqma6: Add WRU-IV baseboard for the TQMa6 SoMStefan Roese2015-07-26-0/+437
| | | | | | | | | This patch adds support for the "OHB System AG" baseboard with is equipped with the TQMa6S SoM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Stefano Babic <sbabic@denx.de>
* Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-07-17-1771/+2544
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| * Merge git://git.denx.de/u-boot-x86Tom Rini2015-07-15-1623/+2072
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| | * pci: Disable expansion ROM address decoding when signature check failsBin Meng2015-07-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should not leave the expansion ROM address window open when there is not a valid ROM. Suggested-by: Matt Porter <mporter@konsulko.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| | * pci: Configure expansion ROM during auto config processBin Meng2015-07-14-40/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| | * drivers: block: Remove the ata_piix driverBin Meng2015-07-14-789/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver was originally added to support the native IDE mode for Intel chipset, however it has some bugs like not supporting ATAPI devices, endianness issue, or even broken build when CONFIG_LAB48. Given no board is using this driver as of today, rather than fixing all these issues we just remove it from the source tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Adjust config option order in defconfig for Crown Bay and MinnowmaxBin Meng2015-07-14-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig' result so that the config option order matches Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * tools: ifdtool: Write correct offset on 32-bit machineBin Meng2015-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 32-bit machine strtol() returns LONG_MAX which is 0x7fffffff, which is wrong for u-boot.rom components like u-boot-x86-16bit.bin. Change to use strtoll() so that it works on both 32-bit and 64-bit machines. Reported-by: Fei Wang <wangfei.jimei@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add binary blob checksums for Minnowboard MAXSimon Glass2015-07-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To try to reduce the pain of confusion of binary blobs, add MD5 checksums for the current versions. This may worsen the situation as new versions appear, but it should still be possible to obtain these versions, and thus get a working setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass2015-07-14-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * dm: x86: minnowmax: Move PCI to use driver modelSimon Glass2015-07-14-47/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * x86: pci: Tidy up the generic x86 PCI driverSimon Glass2015-07-14-27/+8
| | | | | | | | | | | | | | | | | | | | | | | | This driver should use the x86 PCI configuration functions. Also adjust its compatible string to something generic (i.e. without a vendor name). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Add ROM image description for minnowmaxSimon Glass2015-07-14-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | The layout of the ROM is a bit hard to discover by reading the code. Add a table to make it easier. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * dm: spi: Enable environment for minnowmaxSimon Glass2015-07-14-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable a SPI environment and store it in a suitable place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| | * dm: spi: Correct BIOS protection logic for ICH9Simon Glass2015-07-14-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The logic is incorrect and currently has no effect. Fix it so that we can write to SPI flash, since by default it is write-protected. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
| | * dm: spi: Correct status register access widthSimon Glass2015-07-14-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The status register on ICH9 is a single byte, so use byte access when writing to it, to avoid updating the control register also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| | * x86: Configure VESA parameters before loading Linux kernelBin Meng2015-07-14-2/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
| | * x86: crownbay: Enable graphics supportBin Meng2015-07-14-14/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable graphics support on Intel Crown Bay board With the help of vgabios for Intel TunnelCreek IGD. Tested with an external LVDS panel connected to X4 connector and SDVO adapter connected to X9 connector on the board. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Remove MARK_GRAPHICS_MEM_WRCOMBBin Meng2015-07-14-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code, hence remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Move VGA option rom macros to KconfigBin Meng2015-07-14-11/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: cmd_mtrr: Improve MTRR list informationBin Meng2015-07-14-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Print the meaningful base address and mask of an MTRR range without showing the memory type encoding or valid bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: queensbay: Change CPU_ADDR_BITS to 32Bin Meng2015-07-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Per CPUID:80000008h result, the maximum physical address bits of TunnelCreek processor is 32 instead of default 36. This will fix the incorrect decoding of MTRR range mask. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Setup fixed range MTRRs for legacy regionsBin Meng2015-07-14-11/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | We should setup fixed range MTRRs for some legacy regions like VGA RAM and PCI ROM areas as uncacheable. Note FSP may setup these to other cache settings, but we can override this in x86_cpu_init_f(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * video: Add 32-bit color depth support for VBEJian Luo2015-07-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit color depth is configured. Since 24-bit mode already uses 4 bytes internally, it should be OK to just add this option in switch case. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: bios: Allow pci config read/write to host bridge in int1a_handlerJian Luo2015-07-14-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | We should allow pci config read/write to host bridge (b.d.f = 0.0.0) in the int1a_handler() which is a valid pci device. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: bios: Synchronize stack between real and protected modeJian Luo2015-07-14-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | PCI option rom may use different SS during its execution, so it is not safe to assume esp pointed to the same location in the protected mode. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * video: vesa_fb: Look up VGA device by class instead of idBin Meng2015-07-14-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Per PCI spec, VGA device reports its class as standard 030000h in its configuration space, so we can use it to determine if we need run option rom instead of testing the supported vendor/device ids. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dm: pci: Correct bus number when scanning sub-busesSimon Glass2015-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it so that sub-buses are numbered correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * dm: pci: Use the correct hose when configuring devicesSimon Glass2015-07-14-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * x86: queensbay: Change PCIe root ports' interrupt routingBin Meng2015-07-14-10/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far interrupt routing works pretty well for any on-chip devices on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, Linux kernel is smart enough to do interrupt swizzling and figure out device's irq using its parent bridge's interrupt routing info all the way up to its root port. In U-Boot all PCIe root ports' interrupts were routed to PIRQ E/F/G/H before, while actually all PCIe downstream ports received INTx are routed to PIRQ A/B/C/D directly and not configurable. Now we change this mapping so that any external PCIe device can work correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: crownbay: Enable writing MP tableBin Meng2015-07-14-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable writing MP table for Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Update README.x86 for SMP supportBin Meng2015-07-14-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Document U-Boot multi-processor support as well as configuration tables like SFI and MP tables for SMP OS kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Generate a valid MultiProcessor (MP) tableBin Meng2015-07-14-0/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement write_mp_table() to create a minimal working MP table. This includes an MP floating table, a configuration table header and all of the 5 base configuration table entries. The I/O interrupt assignment table entry is created based on the same information used in the creation of PIRQ routing table from device tree. A check duplicated entry logic is applied to prevent writing multiple I/O interrupt entries with the same information. Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we need actually write the MP table at the F seg, just like we did for PIRQ routing and SFI tables. With MP table existence, linux kernel will switch to I/O APIC and local APIC to process all the peripheral interrupts instead of 8259 PICs. This takes full advantage of the multicore hardware and the SMP kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add MultiProcessor (MP) table APIsBin Meng2015-07-14-0/+688
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MP table provides a way for the operating system to support for symmetric multiprocessing as well as symmetric I/O interrupt handling with the local APIC and I/O APIC. We provide a bunch of APIs for U-Boot to write the floating table, configuration table header as well as base and extended table entries. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Remove inline for lapic access routinesBin Meng2015-07-14-151/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove inline for lapic access routines and expose lapic_read() & lapic_write() as APIs to read/write lapic registers. Also move stop_this_cpu() to mp_init.c as it has nothing to do with lapic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add I/O APIC register access routinesBin Meng2015-07-14-1/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | I/O APIC registers are addressed indirectly. Add io_apic_read() and io_apic_write() routines to help register access. Two macros for I/O APIC ID and version register offset are also added. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-12-02 04:46:05 +0000