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* blackfin: Change SMC dcplb entry flag to cover 16M address regionSonic Zhang2014-02-07-1/+2
| | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* blackfin: init bss earlyBob Liu2014-02-07-1/+1
| | | | | Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* blackfin: The logic of the BF609 macro is opposite.Sonic Zhang2014-02-07-3/+3
| | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* include/usb/s3c_udc.h: Add <asm/sizes.h>Tom Rini2014-02-06-0/+1
| | | | | | | With e0059ea switching to using SZ_1K, we need to #include <asm/sizes.h> here for everyone to build still. Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'fpga' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-06-0/+19
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| * fpga: zynqpl: Add support for zc7015 deviceMichal Simek2014-02-06-0/+9
| | | | | | | | | | | | Just extend tables with this new device. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * fpga: zynq: Correct fpga load when buf is not alignedNovasys Ingenierie2014-02-06-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is not aligned, new_buf address became greater then buf_start address and the load_word loop corrupts bit file data. A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data before buf but permits to load correctly. Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | usb: mv_udc: Rename to ci_udcMarek Vasut2014-02-06-111/+111
| | | | | | | | | | | | | | | | | | | | The mv_udc is not marvell-specific anymore. The mv_udc is used to drive generic ChipIdea CI13xxx series OTG cores, so rename the driver to ci_udc instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Stefano Babic <sbabic@denx.de>
* | usb:gadget:f_thor: cosmetic: Remove debug memsetLukasz Majewski2014-02-06-2/+0
| | | | | | | | | | | | | | | | Apparently debug memset (with a 0x55 value) has been overlooked in the f_thor code. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:gadget:f_thor: Allocate request up to THOR_PACKET_SIZE not ep->maxpacketLukasz Majewski2014-02-06-1/+1
| | | | | | | | | | | | | | | | Now it is possible to allocate static request - which receives data from the host (OUT transaction) to the size of THOR packet. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:udc:samsung: Zero copy approach for data passed to Samsung's UDC driverLukasz Majewski2014-02-06-44/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Samsung's UDC driver is not anymore copying data from USB requests to aligned internal buffers. Now it works directly in data allocated in the upper layers like UMS, DFU, THOR. This change is possible since those gadgets now must take care to allocate buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE). This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer aligned to cache line in both starting address and its size. Sometimes it is enough to just use memalign() with size being a multiplication of cache line size. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 27.04 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:udc:samsung: Allow burst transfers for non EP0 endpintsLukasz Majewski2014-02-06-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removed obscure restriction on the HW setting of DMA transfers. Before this change each transaction sent up to 512 bytes (with packet count equal to 1) for non EP0 transfer. Now it is possible to setup DMA transaction up to DMA_BUFFER_SIZE. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 20.74 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:udc:samsung: Remove redundant cache operation from Samsung UDC driverLukasz Majewski2014-02-06-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A set of cache operations (both invalidation and flush) were redundant in the S3C HS OTG Samsung driver: 1. s3c_udc_ep0_zlp - to transmit EP0's ZLP packets one don't need to flush the cache (since it is the zero length transmission) 2. s3c_udc_pre_setup and s3c_ep0_complete_out - cache invalidation is not needed when the buffer for OUT EP0 transmission is setup, since no data has yet arrived. Cache cleanups presented above don't contribute much to transmission speed up, hence shall be regarded as cosmetic changes. 3. setdma_rx - here the s3c UDC driver's internal buffers were invalidated. This call is not needed anymore since we reuse the buffers passed from gadgets. This is a key contribution to transmission speed improvement. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurements: Base values (without improvement): Transmission speed: 9.51 MiB/s After the change: Transmission speed: 10.15 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | usb:gadget:ums: Replace malloc calls with memalign to fix cache buffer alignmentLukasz Majewski2014-02-06-2/+2
|/ | | | | | | | Calls to malloc() have been replaced by memalign. It now provides proper buffer alignment. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* config: Fix line lengths in include/config_distro_defaults.hTom Rini2014-02-05-2/+3
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* config: add config_distro_defaults.hDennis Gilmore2014-02-04-0/+55
| | | | | | | | describe a set of default features that distros can rely on being available. having this common definition means that distros can easily support systems implementing them. Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* cmd_pxe.c add any option for filesystem with sysboot uses generic loadDennis Gilmore2014-02-04-3/+19
| | | | Signed-off-by: Dennis Gilmore <dennis@ausil.us>
* Merge branch 'serial' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-1/+13
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| * serial: uartlite: Reset RX/TX in initMichal Simek2014-02-04-1/+13
| | | | | | | | | | | | Just to be sure that there is no pending data. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'net' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-0/+9
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| * | net: axi_emac: Check if phy was correctly detectedMichal Simek2014-02-04-0/+4
| | | | | | | | | | | | | | | | | | | | | As tsec and fm drivers checking phydev->link ensure that u-boot don't try access device if link is not ready. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | net: gem: Check if phy was correctly detectedMichal Simek2014-01-21-0/+5
| |/ | | | | | | | | | | | | As tsec and fm drivers checking phydev->link ensure that u-boot don't try access device if link is not ready. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-3/+231
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| * | microblaze: Add SPL supportMichal Simek2014-02-04-2/+219
| | | | | | | | | | | | | | | | | | | | | Add support for U-BOOT SPL. NOR and RAM mode are supported. There are 3 images in NOR flash. u-boot.img, dtb and kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | microblaze: Enable buffer write for NOR flashesMichal Simek2014-02-04-1/+2
| | | | | | | | | | | | | | | | | | It speeds up writing a lot. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | microblaze: Report priviledged or stack protection exceptionMichal Simek2014-02-04-0/+3
| | | | | | | | | | | | | | | | | | Just list one more exception. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | microblaze: Show u-boot bannerMichal Simek2014-02-04-0/+7
| | | | | | | | | | | | | | | | | | It is nice to see u-boot version. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'clk' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-0/+60
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| * | | common: Add new clk commandMichal Simek2014-02-04-0/+60
| |/ / | | | | | | | | | | | | | | | | | | | | | Command provides just dump subcommand for showing clock frequencies in a soc. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-02-04-361/+1230
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| * | | driver/ifc:Change accessor function to take care of endiannessPrabhakar Kushwaha2014-02-03-164/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So update acessor functions with common IFC acessor functions to take care both type of endianness. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | kmp204x: initial support for PCIe FPGA configurationValentin Longchamp2014-02-03-1/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PEXHC PCIe configuration mechanism ensures that the FPGA get configured at power-up. Since all the PCIe devices should be configured when the kernel start, u-boot has to take care that the FPGA gets configured also in other reset scenarios, mostly because of possible configuration change. The used mechanism is taken from the km_kirkwood design and adapted to the kmp204x case (slightly different HW and PCIe configuration). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | kmp204x: enable support for SPANSION SPI NORValentin Longchamp2014-02-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new prototype and the final series was moved from Micron to Spansion to have a better reset sequence that is easier to support. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | KM: add the KM_UBI_PART_BOOT_OPTS #defineValentin Longchamp2014-02-03-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This define can be used if the ubi boot partition (defined for all Keymile boards with KM_UBI_PARTITION_NAME_BOOT #define to ubi0) needs some additionnal boot options. This is the case for the kmp204x boards since u-boot does not support NAND Flash subpage accesses on this platform, an additionnal argument that defines the VID offstet must be given to the kernel. The UBI cmd line option now looks like this "ubi.mtd=ubi0,2048" on this platform. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | kmp204x: update I2C field of RCWValentin Longchamp2014-02-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the previous HW revision (now unsupported), there was a need for external DMA signals and thus the I2C3/4 signals were used DMA1_DONE/ACK/REQ. These signals now are configured as GPIO[16:19]. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | kmp204x: add support for the kmcoge4 boardValentin Longchamp2014-02-03-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kmcoge4 board is the product board derived from the kmlion1 prototype. The main difference between the 2 boards is that the kmcoge4 does not configure the Local Bus controller for LCS2. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: Minor change to boards.cfg to keep targets in order] Signed-off-by: York Sun <yorksun@freescale.com>
| * | | kmp204x: implement workaround for A-006559Valentin Longchamp2014-02-03-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the errata, some bits of an undocumented register in the DCSR must be set for every core in order to avoid a possible data or instruction corruption. This is required for the 2.0 revision of the P2041 that should be used as soon as available in our design. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | kmp204x: I2C deblocking supportRainer Boschung2014-02-03-3/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for using some GPIOs that are connected to the I2C bus to force the bus lines state and perform some bus deblocking sequences. The KM common deblocking algorithm from board/keymile/common/common.c is used. The GPIO lines used for deblocking the I2C bus are some external GPIOs provided by the QRIO CPLD: - SCL = GPIOA_20 - SDA = GPIOA_21 The QRIO GPIOs act in an open-drain-like manner, for 0 the line is driven low and for 1 the GPIO is set as input and the line gets pulled-up. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | kmp204x: introduce QRIO GPIO functionsValentin Longchamp2014-02-03-57/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QRIO GPIO functions can be of general interest. They are thus added to a qrio.c and their prototype are available from kmp204x.h. The QRIO prst function are also included in this file, as well as the functions required for the I2C deblocking support (open-drain). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: Remove extra blank line in board/keymile/kmp204x/qrio.c] Signed-off-by: York Sun <yorksun@freescale.com>
| * | | kmp204x: support for QRIO1 bootcounterRainer Boschung2014-02-03-22/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make use of the QRIO1 32bit register at 0x20 as bootcounter register Check for BOOTCOUNT_MAGIC pattern when before bootcounter value is read Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: Minor change to commit message] Signed-off-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t104xrdb: Add basic ethernet supportPriyanka Jain2014-02-03-6/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This covers only non-L2 switch ethernet interfaces i.e. RGMII and SGMII interface for both T1040RDB and T1042RDB_PI T1040RDB is configured as serdes protocol 0x66 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 1 SGMII on DTSEC3 T1042RDB_PI is configured as serdes protocol 0x06 which can support following interfaces 2 RGMIIS on DTSEC4, DTSEC5 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: Minor change in commit message] Signed-off-by: York Sun <yorksun@freescale.com>
| * | | powerpc/usb: Enable dual phy for T1040Nikhil Badola2014-02-03-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE macro for enabling dual phy in t1040 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t104xrdb: Update T1042RDB.h in config folderPrabhakar Kushwaha2014-02-03-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add usb2 node entry to hwconfig default Remove DDR controller interleaving from hwconfig Move SPI related macros out of "#ifdef CONFIG_SPIFLASH" Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible in u-boot Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Fix commit message] Signed-off-by: York Sun <yorksun@freescale.com>
| * | | powerpc/t104xrdb: Update T1040RDB.h in config folderPriyanka Jain2014-02-03-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add usb2 node entry in "hwconfig string" Remove controller interleaving from hwconfig string as T1040 has only one DDR conroller SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH are move outside so that they are defined for all cases as these macros are also used by other u-boot code Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: Minor change to commit message] Signed-off-by: York Sun <yorksun@freescale.com>
| * | | boards/t1040qds: Adds ethernet support for T1040Prabhakar Kushwaha2014-02-03-3/+563
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx: Update serdes protocols for T1040Prabhakar Kushwaha2014-02-03-43/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 has only one SerDes block. so update the code accordingly. Also, add support of SerDes Protocol 0x00, 0x06, 0x40, 0x69 0x85, 0xA7 and 0xAA Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx:Fix README to show correct flash memory mapPrabhakar Kushwaha2014-02-03-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to increased size of u-boot, FMAN ucode start address has been shifted by 256KB causing a overlap with rootfs start address. Update rootfs start address to reflect correct memory map. Also fix minor typo in README Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | driver/fsl_pci:Update print to display PCIe generationPrabhakar Kushwaha2014-02-03-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current print only display width of PCIe device. Add print to display PCIe generation supported by the device. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx: Update LIODNs for T1040poonam aggrwal2014-02-03-36/+0
| |/ / | | | | | | | | | | | | | | | | | | | | | Removed LIODNs for RMAN, RIO, 10G. T1040 has 10 QMAN portals so assigned LIODNs accordingly. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | pxe: implement fdtdir extlinux.conf tagStephen Warren2014-02-04-6/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | People who write (or scripts that auto-generate) extlinux.conf don't want to know about HW-specific information such as FDT filenames. Create a new extlinux.conf tag "fdtdir" that specifies only the directory where FDT files are located, and defer all knowledge of the filename to U-Boot. The algorithm implemented is: ========== if $fdt_addr_r is set: if "fdt" tag was specified in extlinux.conf: load the FDT from the filename in the tag else if "fdtdir" tag was specified in extlinux.conf: if "fdtfile" is set in the environment: load the FDT from filename in "$fdtfile" else: load the FDT from some automatically generated filename if no FDT file was loaded, and $fdtaddr is set: # This indicates an FDT packaged with firmware use the FDT at $fdtaddr ========== A small part of an example /boot/extlinux.conf might be: ========== LABEL primary LINUX zImage FDTDIR ./ LABEL failsafe LINUX bkp/zImage FDTDIR bkp/ ========== ... with /boot/tegra20-seaboard.dtb or /boot/bkp/tegra20-seaboard.dtb being loaded by the sysboot/pxe code. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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