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| * | SECURE BOOT - Removed deletion of TLB entries codeRuchika Gupta2013-05-24-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/b4860qds: Add LAW Target ID and Create LAW entry for MapleShaveta Leekha2013-05-24-0/+14
| | | | | | | | | | | | | | | Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p5040: fix mdio mux for 10G portShaohui Xie2013-05-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in eth port enum structure, it will assign mdio mux depend on this assumption. This is not true with Fman V3, which added more 1G ports after port DTSEC5 in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux. So we use dynamic index for 10G ports instead of hardcoded enum value when doing mdio mux for 10G ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.hPoonam Aggrwal2013-05-24-24/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify the defines. - Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere. - defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G. Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | sf: spansion: Add support for S25FL128SXie Xiaobo2013-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash memory have the same device ID and Memory architecture. So they can use the same config parameters. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p2041: fix serdes reference clock frequency display for PC boardShaohui Xie2013-05-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PC board has different serdes clock setting with PB board, it uses same serdes frequency setting on bank2 as on bank1. PC board can be distingushed from PB board by checking CPLD version, if running on PC board, then fix the serdes reference clock frequency of bank2. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/b4860: fix for Serdes connectivity to SFP'sShaveta Leekha2013-05-24-12/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Crossbar switches were wrongly programmed to route the CPRI lanes to SFP as the connectivity table was not correct. Modified it correctly for SFPs connections. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4240qds: fix PHY reset timeout issueShengzhou Liu2013-05-24-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | QSGMII card has different PHY address against previous SGMII card. We check the type of card in slots and set correct PHY address to avoid complainning "PHY reset timed out" during u-boot booting up. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4qds: Add SW7[4] in the DIP switch displayYork Sun2013-05-24-2/+3
| | | | | | | | | | | | | | | | | | | | | SW7[4] is the new bit which controls the mapping of eMMC vs SDHC. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Enable XAUI interface for B4860QDSSuresh Gupta2013-05-24-3/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32MStephen George2013-05-24-7/+9
| | | | | | | | | | | | | | | | | | | | | Debug trace buffers are memory mapped in DCSR space beyond 4M. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p5040: enable PBL tool supportShaohui Xie2013-05-24-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Provided a default RCW for P5040, then it can use PBL to build ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4qds: use clock measurement for sysclk and ddr clockEd Swarthout2013-05-24-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use QIXIS measurement registers to obtain sysclk and ddr clock. This allows using non-standard clock speeds, set by directly writing to clock chip or store the values in qixis clock data eeprom. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/qixis: add clock measurement registersEd Swarthout2013-05-24-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QIXIS includes frequency measurement functions for each major processor clock input. After reset (and after clocks are stable), QIXIS measures the clocks against a reference frequency and stores the results in CLK_FREQ registers. A base register supplies a multiplier which allows directly obtaining the measured value, without requiring knowledge of the target system or QIXIS core frequency. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc8xxx: Allow DDR overclockYork Sun2013-05-24-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow DDR clock runs faster than SPD specifes. This may cause memory failure, but the user should know what is going to happen when using higher than expected DDR clock. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/chassis2: Change core numbering schemeYork Sun2013-05-24-58/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc8xxx: Add T1040 and variant SoCsYork Sun2013-05-24-0/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.hYork Sun2013-05-24-33/+10
| | | | | | | | | | | | | | | | | | | | | | | | T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/p5040: enable NAND, SD, SPI boot supportShaohui Xie2013-05-24-0/+3
| | | | | | | | | | | | | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Add e6500 L2 replacement policy selectionJames Yang2013-05-24-1/+11
| | | | | | | | | | | | | | | | | | | | | This is compile-time config. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | T4240/ramboot: enable PBL tool for T4240Shaohui Xie2013-05-24-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use PBL tool to produce the ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4240qds: Add VDD overrideYork Sun2013-05-24-2/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow VDD voltage overriding with a command. This is an add-on feasture of VID. To override VDD, use command vdd_override with the value of voltage in mV, for example vdd_override <voltage in mV, eg. 1050> The above example will set the VDD to 1.050 volt. Any wrong value out of range of 0.8188 to 1.2125 volt or invalid string is ignored. In addition to the command, if overriding VDD is needed earlier in booting process, save an variable and reboot: setenv t4240qds_vdd_mv <voltage in mV> saveenv Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc85xx: check if core is disabled for showing statusYork Sun2013-05-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | "cpu <num> status" should check if core is disabled before printing the spin table location. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | net/phy: fix select line for TN80xxShaohui Xie2013-05-24-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TN80xx has same PHY ID as TN2020, but it needs different setting to register 30.93 which used to select line, so we read register 30.32 which has bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2, for TN80xx we will get 5 or 4. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Enable L2 cache parity/ECC error checkingJames Yang2013-05-24-2/+2
| | | | | | | | | | | | | | | Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/t4240qds: Add board detail for bdinfo commandYork Sun2013-05-24-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Print more detail information including core voltage, RCW source, switch settings, etc. with bdinfo command. Signed-off-by: York Sun <yorksun@freescale.com> CC: Wolfgang Denk <wd@denx.de> CC: Tom Rini <trini@ti.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | common: Update cmd_bdinfo for PPCYork Sun2013-05-24-0/+5
| | | | | | | | | | | | | | | | | | | | | Add board detail function to print more individual board information. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | cmd_mem: fix cp commandMasahiro Yamada2013-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "cp" command has not worked since commit 0628ab8ec59834f98ede267edd21ddb8ba0bb57b, because of the following lines, which set the destination and the source to the same address. buf = map_sysmem(addr, bytes); src = map_sysmem(addr, bytes); Tested-by: Tom Rini <trini@ti.com> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ext4: assign get_fs()->dev_desc before using itStephen Warren2013-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 50ce4c0 "fs/ext4: Support device block sizes != 512 bytes" modified ext4fs_set_blk_dev() to calculate total_sect based on get_fs()->dev_desc->log2blksz rather than SECTOR_SIZE. However, this value wasn't yet assigned. Move the assignment earlier so the code doesn't crash or hang. Cc: Egbert Eich <eich@suse.com> Tested-by: Tom Rini <trini@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | cfi_flash: return NULL for invalid base address inputMasahiro Yamada2013-05-23-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When base address given was out of valid flash address ranges, flash_get_info() function returned the pointer to the last element of flash_info[i] array. This patch changes this function to return NULL pointer in such a case, which is more correct behaviour. The function flash_protect_default() calls flash_protect() immediately after flash_get_info() invocation. With this correction, flash_protect() function would be able to return soon, for NULL flash_info. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | cosmetic: cfi_flash: delete a space after an unary operatorMasahiro Yamada2013-05-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Linux Kernel Documentation/CodingStyle says: Do not add a space after unary operators such as &, *, ... Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | cfi_flash: Fix unaligned accesses to cfi_qry structureAndrew Gabbasov2013-05-23-13/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Packed structure cfi_qry contains unaligned 16- and 32-bits members, accessing which causes problems when cfi_flash driver is compiled with -munaligned-access option: flash initialization hangs, probably due to data error. Since the structure is supposed to replicate the actual data layout in CFI Flash chips, the alignment issue can't be fixed in the structure. So, unaligned fields need using of explicit unaligned access macros. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Reviewed-By: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Stefan Roese <sr@denx.de>
| * | Update MAINTAINERS file for sandboxSimon Glass2013-05-17-0/+11
| | | | | | | | | | | | | | | | | | This currently has no maintainer listed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | Update MAINTAINERS file for x86Simon Glass2013-05-17-3/+13
| | | | | | | | | | | | | | | | | | This still shows the previous maintainer. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | .gitignore: add GNU GLOBAL filesMasahiro Yamada2013-05-17-0/+6
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | fdt_support: Use CONFIG_NR_DRAM_BANKS if definedDoug Anderson2013-05-17-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | It appears that there are some cases where we have more than 4 banks of memory. Use CONFIG_NR_DRAM_BANKS if it's defined to handle this. This will take up a little extra stack space (64 bytes extra if we go up to 8 banks), but that seems OK. Signed-off-by: Doug Anderson <dianders@chromium.org>
| * | bootm: Avoid 256-byte overflow in fixup_silent_linux()Doug Anderson2013-05-17-12/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes fixup_silent_linux() use malloc() to allocate its working space, meaning that our maximum kernel command line should only be limited by malloc(). Previously it was silently overflowing the stack. Note that nothing about this change increases the kernel's maximum command line length. If you have a command line that is >256 bytes it's up to you to make sure that kernel can handle it. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * | README: Correct reference for CONFIG_SUPPORT_RAW_INITRDTom Rini2013-05-16-1/+1
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * | powerpc/esdhc: Correct judgement for DATA PIO modeHaijun.Zhang2013-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The logic for the whether to configure for polling or DMA was mistakenly reversed in this patch: Commit 7b43db92110ec2f15c5f7187a165f2928464966b drivers/mmc/fsl_esdhc.c: fix compiler warnings Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Sun Yusong-R58495 <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | mmc: update Faraday FTSDC010 for rw performanceKuo-Jung Su2013-05-15-697/+400
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Faraday FTSDC010 is a MMC/SD host controller. Although there is already a driver in current u-boot release, which is modified from eSHDC and contributed by Andes Tech. Its performance is too terrible on Faraday A36x SoC platforms, so I turn to implement this new version of driver which is 10+ times faster than the old one. It's carefully designed to be compatible with Andes chips, so it should be safe to replace it. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-15-227/+1154
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| | * | T4240/eth: fix SGMII card PHY addressShaohui Xie2013-05-14-4/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QSGMII card assumed to be used by default, but if SGMII card is used, it will use different PHY address, but we don't know which card is used until we access PHY on the card. So we check the card type slot by slot, if we can read a PHY ID by reading a SGMII PHY address on a slot, then the slot must have a SGMII card pluged, we mark all ports on that slot, and fix dts to use the SGMII card PHY address when doing dts fixup for the marked ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/t4qds: Fix disabling remote I2C connectionEd Swarthout2013-05-14-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only clear IRE bit in qixis brdcfg5 register and keep other bits unchanged. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/b4860qds: Assign DDR address in board fileYork Sun2013-05-14-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address. This is the requirement for DSP cores to run in 32-bit address space. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/mpc8xxx: Allow board file to override DDR address assignmentYork Sun2013-05-14-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This gives boards flexibility to assign other than default addresses to each DDR controller. For example, DDR controler 2 can have 0 as the base and DDR controller 1 has higher memory. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/mpc85xx: Update workaround for DDR erratum A-004934York Sun2013-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The workaround has been updated to use a slightly different magic number. Change from 0x00003000 to 0x30003000. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.cRoy Zang2013-05-14-21/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY initialization can be reused in kernel without “usb start” command. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | T4240/net: use QSGMII card PHY address by defaultShaohui Xie2013-05-14-57/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card PHY address is variable depends on different slot. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | net/phy: add VSC8574 supportShaohui Xie2013-05-14-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes interfaces for quad-port dual media capability. This driver supports SGMII and QSGMII MAC mode. For now SGMII mode is tested. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * | powerpc/85xx: fix build error introduced by serdes_get_prtclShengzhou Liu2013-05-14-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed unused declare serdes_get_prtcl() which was no longer needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-11-01 00:27:53 +0000