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* Revert "image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro."Masahiro Yamada2016-05-31-12/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 56adbb38727320375b2f695bd04600d766d8a1b3. Since commit 56adbb387273 ("image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro."), I found my boards fail to boot Linux because the commit changed the logic of macros it touched. Now, IMAGE_ENABLE_RAMDISK_HIGH and IMAGE_BOOT_GET_CMDLINE are 0 for all the boards. As you can see in include/linux/kconfig.h, CONFIG_IS_ENABLE() (and IS_ENABLED() as well) can only take a macro that is either defined as 1 or undefined. This is met for boolean options defined in Kconfig. On the other hand, CONFIG_SYS_BOOT_RAMDISK_HIGH and CONFIG_SYS_BOOT_GET_CMDLINE are defined without any value in arch/*/include/asm/config.h . This kind of clean-up is welcome, but the options should be moved to Kconfig beforehand. Moreover, CONFIG_IS_ENABLED(SPL_CRC32_SUPPORT) looks weird. It should be either CONFIG_IS_ENABLED(CRC32_SUPPORT) or IS_ENABLED(CONFIG_SPL_CRC32_SUPPORT). But, I see no define for CONFIG_SPL_CRC32_SUPPORT anywhere. Likewise for the other three. The logic of IMAGE_OF_BOARD_SETUP and IMAGE_OF_SYSTEM_SETUP were also changed for SPL. This can be a problem for boards defining CONFIG_SPL_OF_LIBFDT. I guess it should have been changed to IS_ENABLED(CONFIG_OF_BOARD_SETUP). In the first place, if we replace the references in C code, the macros IMAGE_* will go away. if (IS_ENABLED(CONFIG_OF_BOARD_SETUP) { ... } Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-05-30-32/+685
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| * x86: baytrail: acpi: Fix I/O APIC ID in the MADT tableBin Meng2016-05-30-1/+1
| | | | | | | | | | | | | | | | So far this is hardcoded to 2, but it should really be read from the I/O APIC register. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Enable ACPI table generationBin Meng2016-05-30-1/+34
| | | | | | | | | | | | | | Enable ACPI table generation by creating a DSDT table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Generate ACPI FADT/MADT tablesBin Meng2016-05-30-0/+164
| | | | | | | | | | | | | | Generate quark platform-specific FADT/MADT tables. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add platform ASL filesBin Meng2016-05-30-0/+433
| | | | | | | | | | | | | | | | This adds basic quark platform ASL files. They are intended to be included in dsdt.asl of any board that is based on this platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Prepare device.h for inclusion by ASLBin Meng2016-05-30-6/+15
| | | | | | | | | | | | | | | | | | There is a device.h for quark on-chip devices, mainly for definitions of internal PCI device numbers, but it's not ready to be included by ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * acpi: Pass -D__ASSEMBLY__ when compiling ASL filesBin Meng2016-05-30-1/+1
| | | | | | | | | | | | | | | | | | | | ASL files may include various U-Boot header files, but IASL compiler does not understand any C language embedded in these header files. To reuse those header files for ASL compiling, use __ASSEMBLY__ in the header files to exclude everything that is not liked by IASL. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: acpi: Make irqroute.asl commonBin Meng2016-05-30-2/+2
| | | | | | | | | | | | | | | | | | | | The irqroute.asl file is already common enough to all x86 platforms. Platform ASL files need only provide a irqroute.h to describe how internal PCI devices and PCIe downstream port devices' INTx pins are routed to which PIRQ pin. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: acpi: Create a common irqlinks ASL fileBin Meng2016-05-30-21/+35
| | | | | | | | | | | | | | | | | | | | | | Move the irqlinks.asl file currently in the BayTrail directory to a common place to be shared among all x86 platforms. As the PIRQ routing control programming interface is common to Intel chipsets, leave the common part in the common file, and move the platform specific part to the platform files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-05-27-510/+1272
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For odroid-c2 (arch-meson) for now disable designware eth as meson now needs to do some harder GPIO work. Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: lib/efi_loader/efi_disk.c Modified: configs/odroid-c2_defconfig
| * | dm: rockchip: Enable CONFIG_BLKSimon Glass2016-05-27-0/+3
| | | | | | | | | | | | | | | | | | | | | Enable CONFIG_BLK to move to using driver model for block devices. This affects MMC booting in SPL, as well as MMC access in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: Use cfg directly in mmc_bind()Simon Glass2016-05-27-1/+1
| | | | | | | | | | | | | | | | | | This small change tidies up the code slightly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: Fix up mmc_bread/bwrite() prototypes for SPLSimon Glass2016-05-27-0/+14
| | | | | | | | | | | | | | | | | | | | | When these functions are not compiled in, we still need to declare the correct function signature to avoid a build warnings in SPL. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: rockchip: mmc: Allow use of CONFIG_BLKSimon Glass2016-05-27-0/+31
| | | | | | | | | | | | | | | | | | Allow driver model to be used for block devices in the rockchip mmc driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: dwmmc: Support CONFIG_BLKSimon Glass2016-05-27-15/+34
| | | | | | | | | | | | | | | | | | Add support for using driver model for block devices in this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: mmc: spl: Add support for CONFIG_BLKSimon Glass2016-05-27-5/+4
| | | | | | | | | | | | | | | | | | Allow driver model to be used for block devices in SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: efi: Update for CONFIG_BLKSimon Glass2016-05-27-16/+47
| | | | | | | | | | | | | | | | | | | | | | | | This code does not currently build with driver model enabled for block devices. Update it to correct this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexander Graf <agraf@suse.de>
| * | dm: mmc: Convert sdhci to support CONFIG_BLKSimon Glass2016-05-27-1/+1
| | | | | | | | | | | | | | | | | | Update sdhci.c so that it works with driver model enabled for block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: env: mmc: Convert env_mmc to support CONFIG_BLKSimon Glass2016-05-27-4/+4
| | | | | | | | | | | | | | | | | | | | | Update the MMC environment code so that it works with driver-model enabled for block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Drop SPL GPIO support for rk3288Simon Glass2016-05-27-1/+0
| | | | | | | | | | | | | | | | | | This is not currently used and saves a little over 1KB of SPL image size. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: video: Flush the cache when the display is updatedSimon Glass2016-05-27-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable this option to correct display artifacts when a write-back cache is in use. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Drop unnecessary SPL propertiesSimon Glass2016-05-27-1/+1
| | | | | | | | | | | | | | | | | | | | | While we consider whether to drop use of DT in SPL, remove some unwanted properties. This reduces SPL size by about 250 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Check image name for the rksd imageSimon Glass2016-05-27-6/+1
| | | | | | | | | | | | | | | | | | | | | We need a correct name (rk3288, rk3036) so check this to avoid a crash later. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | mmc: Use byte array for multipliersSimon Glass2016-05-26-1/+1
| | | | | | | | | | | | | | | | | | | | | We don't need an int since no value is over 80. This saves a small amount of SPL space (about 44 bytes). Signed-off-by: Simon Glass <sjg@chromium.org>
| * | mmc: Drop dead mmc code for non-generic MMCSimon Glass2016-05-26-66/+0
| | | | | | | | | | | | | | | | | | | | | All boards that use MMC define CONFIG_GENERIC_MMC now, so we can drop this old code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | mmc: Drop mmc_register()Simon Glass2016-05-26-10/+0
| | | | | | | | | | | | | | | | | | This function is no longer used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | reset: Drop the reset failure messageSimon Glass2016-05-26-1/+1
| | | | | | | | | | | | | | | | | | This adds to code size and is not needed, since hang() will print a message. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | tiny-printf: Support snprintf()Simon Glass2016-05-26-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | Add a simple version of this function for SPL. It does not check the buffer size as this would add to the code size. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * | tiny-printf: Tidy up a few nitsSimon Glass2016-05-26-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Rename 'w' to 'width' to make it more obvious what it is used for - Use bool and int types instead of char to avoid register-masking on 32-bit machines Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * | arm: rpi: Define CONFIG_TFTP_TSIZE to show tftp size infoSimon Glass2016-05-26-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This shows a proper progress display and the total amount of data transferred. Enable it for Raspberry Pi. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
| * | mailbox: implement a sandbox testStephen Warren2016-05-26-0/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a sandbox mailbox implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> # v1
| * | Add a mailbox driver framework/uclassStephen Warren2016-05-26-0/+431
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A mailbox is a hardware mechanism for transferring small message and/or notifications between the CPU on which U-Boot runs and some other device such as an auxilliary CPU running firmware or a hardware module. This patch defines a standard API that connects mailbox clients to mailbox providers (drivers). Initially, DT is the only supported method for connecting the two. The DT binding specification (mailbox.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | Rename reset to sysresetStephen Warren2016-05-26-315/+316
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current reset API implements a method to reset the entire system. In the near future, I'd like to introduce code that implements the device tree reset bindings; i.e. the equivalent of the Linux kernel's reset API. This controls resets to individual HW blocks or external chips with reset signals. It doesn't make sense to merge the two APIs into one since they have different semantic purposes. Resolve the naming conflict by renaming the existing reset API to sysreset instead, so the new reset API can be called just reset. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | sunxi: gpio: convert bind() to use driver dataStephen Warren2016-05-26-40/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the DM core sets driver_data before calling bind(), this driver can make use of driver_data to determine the set of child devices to create, rather than manually re-implementing the matching logic in code. Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
| * | dm: allow setting driver_data before/during bindStephen Warren2016-05-26-14/+62
| |/ | | | | | | | | | | | | | | | | | | | | This will allow a driver's bind function to use the driver data. One example is the Tegra186 GPIO driver, which instantiates child devices for each of its GPIO ports, yet supports two different HW instances each with a different set of ports, and identified by the udevice_id .data field. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-05-27-8/+182
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| * | rockchip: rock2: dts: use status = "okay" not okSjoerd Simons2016-05-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | u-boot only recognize okay to enable a node (Linux seems to be more lenient here). So use okay instead. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288-firefly: Add gmac definitionSjoerd Simons2016-05-27-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | Add a definition for the gmac interface to the firefly device-tree. Copied verbatim from the linux kernel. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: grf: Define GRF_SOC_CON1 and GRF_SOC_CON3Sjoerd Simons2016-05-27-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | Add definitions for GRF_SOC_CON1 and GRF_SOC_CON3 which contain various GMAC related fields. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add clock support for the gmac ethernet interfaceSjoerd Simons2016-05-27-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Setup the clocks for the gmac ethernet interface. This assumes the mac clock is fed by an external clock which is common on RK3288 based devices. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: pinctrl: support more pinsSjoerd Simons2016-05-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The rgmii_pins node in rk3288.dtsi configures 15 pins. Increase the size of the cell array to accomedate that, otherwise only the first 10 get configured. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | net: designware: support phy reset device-tree bindingsSjoerd Simons2016-05-27-6/+80
| |/ | | | | | | | | | | | | | | | | Add support for the snps,reset-gpio, snps,reset-active-low (optional) and snps,reset-delays-us device-tree bindings. The combination of these three define how the PHY should be reset to ensure it's in a sane state. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: OMAP4+: Fix DPLL programming sequenceLokesh Vutla2016-05-27-3/+5
| | | | | | | | | | | | | | | | | | | | All the output clock parameters of a DPLL needs to be programmed before locking the DPLL. But it is being configured after locking the DPLL which could potentially bypass DPLL. So fixing this sequence. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
* | tools: Add entry for generated tools/bin2header to tools/.gitignoreRobert P. J. Day2016-05-27-0/+1
| | | | | | | | Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* | tools/genboardscfg.py: remove bogus import subprocessMasahiro Yamada2016-05-27-1/+0
| | | | | | | | | | | | | | Since f6c8f38ec601 ("tools/genboardscfg.py: improve performance more with Kconfiglib"), this tool does not use the subprocess module. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | image.h: Tighten up content using handy CONFIG_IS_ENABLED() macro.Robert P. J. Day2016-05-27-57/+12
| | | | | | | | | | | | | | | | | | | | In order for CONFIG_IS_ENABLED(FOO) to work we need to move the changes that CONFIG_FIT_DISABLE_SHA256 makes to be prior to the evaluation by CONFIG_IS_ENABLED(foo) Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> [trini: Move CONFIG_FIT_DISABLE_SHA256 parts to fix build breakage] Signed-off-by: Tom Rini <trini@konsulko.com>
* | arm64: rename __asm_flush_dcache_level to __asm_dcache_levelMasahiro Yamada2016-05-27-6/+6
| | | | | | | | | | | | | | | | | | Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm64: fix comment "flush & invalidate"Masahiro Yamada2016-05-27-2/+2
| | | | | | | | | | | | We should say "clean & invalidate", or simply "flush". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm64: optimize __asm_{flush, invalidate}_dcache_allMasahiro Yamada2016-05-27-8/+2
| | | | | | | | | | | | | | | | | | | | __asm_dcache_all can directly return to the caller of __asm_{flush,invalidate}_dcache_all. We do not have to waste x16 register here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: York Sun <york.sun@nxp.com>
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