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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-05-17 16:38:07 +0900 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-05-27 15:47:55 -0400 |
| commit | 1a021230d37d4f87ec0ca9f4103b582e415f1b76 (patch) | |
| tree | 83d171d301e1ea44d488d3a8baf48fb7849d5f1c | |
| parent | 25828588412c1f951d72e1eda9e4320d422b7be5 (diff) | |
| download | u-boot-imx-1a021230d37d4f87ec0ca9f4103b582e415f1b76.zip u-boot-imx-1a021230d37d4f87ec0ca9f4103b582e415f1b76.tar.gz u-boot-imx-1a021230d37d4f87ec0ca9f4103b582e415f1b76.tar.bz2 | |
arm64: fix comment "flush & invalidate"
We should say "clean & invalidate", or simply "flush".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| -rw-r--r-- | arch/arm/cpu/armv8/cache.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 1c71a2f..6aaecf3 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -19,7 +19,7 @@ * clean and invalidate one level cache. * * x0: cache level - * x1: 0 flush & invalidate, 1 invalidate only + * x1: 0 clean & invalidate, 1 invalidate only * x2~x9: clobbered */ ENTRY(__asm_flush_dcache_level) @@ -62,7 +62,7 @@ ENDPROC(__asm_flush_dcache_level) /* * void __asm_flush_dcache_all(int invalidate_only) * - * x0: 0 flush & invalidate, 1 invalidate only + * x0: 0 clean & invalidate, 1 invalidate only * * clean and invalidate all data cache by SET/WAY. */ |