summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
...
| * | usb: ci_udc: fix probe error cleanupStephen Warren2014-06-11-0/+1
| | | | | | | | | | | | | | | | | | | | | If allocation of the ep0 req fails, clean up all the allocations that were made in ci_udc_probe(). Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | usb: ci_udc: fix freeing of ep0 reqStephen Warren2014-06-11-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ci_ep_alloc_request() avoids allocating multiple request objects for ep0 by keeping a record of the first req allocated for ep0, and always returning that instead of allocating a new req. However, if this req is ever freed, the record of the previous allocation is not cleared, so ci_ep_alloc_request() will keep returning this stale pointer. Fix ci_ep_free_request() to clear the record of the previous allocation. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | usb: ci_udc: call udc_disconnect() from ci_pullup()Stephen Warren2014-06-11-16/+12
| | | | | | | | | | | | | | | | | | | | | ci_pullup()'s !is_on path contains a cut/paste copy of udc_disconnect(). Remove the duplication by simply calling udc_disconnect() instead. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | usb: ci_udc: complete ep0 direction handlingStephen Warren2014-06-01-7/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | handle_setup() currently assumes that the response to a Setup transaction will be an OUT transaction, and any subsequent packet (if any) will be an IN transaction. This appears to be valid in many cases; both USB enumeration and Mass Storage work OK with this restriction. However, DFU uses ep0 to transfer data in both directions. This renders the assumption invalid; when sending data from device to host, the Data Stage is an IN transaction, and the Status Stage is an OUT transaction. Enhance handle_setup() to deduce the correct direction for the USB transactions based on Setup transaction data. ep0's request object only needs to be automatically re-queued when the Data Stage completes, in order to implement the Status Stage. Once the Status Stage transaction is complete, there is no need to re-queue the USB request, so don't do that. Don't sent USB request completion callbacks for Status Stage transactions. These were queued by ci_udc itself, and only serve to confuse the USB function code. For example, f_dfu attempts to interpret the 0-length data buffers for Status Stage transactions as DFU packets. These buffers contain stale data from the previous transaction. This causes f_dfu to complain about a sequence number mismatch. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | usb: ci_udc: pre-allocate ep0 reqStephen Warren2014-06-01-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allocate ep0's USB request object when the UDC driver is probed. This solves a couple of issues in the current code: a) A request object always exists for ep0. Prior to this patch, if setup transactions arrived in an unexpected order, handle_setup() would need to reply to a setup transaction before any ep0 usb_req was created. This issue was introduced in commit 2813006fecda "usb: ci_udc: allow multiple buffer allocs per ep." b) handle_ep_complete no longer /has/ to queue the ep0 request again after every single request completion. This is currently required, since handle_setup() assumes it can find some request object in ep0's request queue. This patch doesn't actually stop handle_ep_complete() from always requeueing the request, but the next patch will. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | usb: ci_udc: use a single descriptor for ep0Stephen Warren2014-06-01-11/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | ci_udc currently points ep->desc at separate descriptors for IN and OUT. These descriptors only differ in the ep address IN/OUT field. Modify the code to use a single descriptor, and change that descriptor's ep address to indicate IN/OUT as required. This removes some data duplication. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | usb: ci_udc: detect queued requests on ep0Stephen Warren2014-06-01-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flipping of ep0 between IN and OUT relies on ci_ep_queue() consuming the current IN/OUT setting immediately. If this is deferred to a later point when the req is pulled out of ci_req->queue, then the IN/OUT setting may have been changed since the req was queued, and state will get out of sync. This condition doesn't occur today, but could if bugs were introduced later, and this error-check will save a lot of debugging time. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | usb: hub: remove CONFIG_USB_HUB_MIN_POWER_ON_DELAYStephen Warren2014-06-01-11/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we wait the correct specification-mandated time at the end of usb_hub_power_on(), I suspect that CONFIG_USB_HUB_MIN_POWER_ON_DELAY has no purpose. For cm_t35.h, we already wait longer than the original MIN_POWER_ON_DELAY, so this change is safe. For gw_ventana.h, we will wait as long as the original MIN_POWER_ON_DELAY iff pgood_delay was at least 200ms. I'm not sure if this is the case or not, hence I've CC'd relevant people to test this change. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | usb: hub: fix power good delay timingStephen Warren2014-06-01-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usb_hub_power_on() currently waits for the maximum of (a) the hub port's power output to become good, (b) the max time the USB specification allows a device to take to connect. However, these two operations must occur in series rather than in parallel. First, the power supply ramps up to the level required to power the USB device, and then the device may take a certain amount of time to connect (assert D+/D- pullups). Related, the maximum time that a device has to assert pullups is 1s not 100ms. This is explained in "Connect Timing ECN.pdf", itself part of usb_20_042814.zip from www.usb.org. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | dfu: Introduction of the "dfu_hash_algo" env variable for checksum method ↵Lukasz Majewski2014-06-01-5/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | setting Up till now the CRC32 of received data was calculated unconditionally. The standard crc32 implementation causes long delay when large images were uploaded. The "dfu_hash_algo" environment variable gives the opportunity to disable on demand the hash (crc32) calculation. It can be done without the need to recompile the u-boot binary. By default the crc32 is calculated, which means that legacy behavior has been preserved. Tests results: 400 MiB ums.img file With crc32 calculation: 65 sec [avg 6.29 MB/s] Without crc32 calculation: 25 sec [avg 16.17 MB/s] Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
* | | Prepare v2014.07-rc3Tom Rini2014-06-10-1/+1
| | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | | net: sh-eth: Fix typo from rESR_RTLF to EESR_RTLFNobuhiro Iwamatsu2014-06-10-1/+1
| | | | | | | | | | | | | | | | | | | | | 'r' of rESR_RTLF is a mistake of E. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | net: sh-eth: Fix coding styleNobuhiro Iwamatsu2014-06-10-22/+22
| | | | | | | | | | | | | | | | | | | | | This fixes checkpatch's warning. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | net: sh-eth: Add support R7S72100 of rmobileNobuhiro Iwamatsu2014-06-10-14/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | The R7S72100 of ARM SoC that Renesas manufactured has one Ether port. This has the same IP SH-Ether. This patch adds support of the R7S72100 in SH-Ether. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-06-08-763/+1918
|\ \ \ | |_|/ |/| |
| * | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-08-155/+624
| |\ \
| | * | arm:am43xx: Add TPS65218 support to scale voltages upTom Rini2014-06-06-7/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This family is supported by the TPS65218 PMIC. Implement a scale_vcores to set the MPU and CORE voltage correctly to the max frequency that is supported (and what we will be scaling them to in setup_dplls()). Signed-off-by: Tom Rini <trini@ti.com>
| | * | power: Add support for the TPS65218 PMICTom Rini2014-06-06-0/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and may be used by TI AM335x SoCs. Signed-off-by: Tom Rini <trini@ti.com>
| | * | arm:am33xx: Add a scale_vcores() hookTom Rini2014-06-06-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to OMAP4/5 we need to scale the voltage up prior to changing the clock frequencies up higher. Add a similar hook to start with. Signed-off-by: Tom Rini <trini@ti.com>
| | * | am43xx: Only read the MPU frequency bits of CTRL_DEV_ATTRTom Rini2014-06-06-1/+4
| | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| | * | board/BuR/tseries: cosmetic changesHannes Petermaier2014-06-06-2/+2
| | | | | | | | | | | | | | | | | | | | Cc: trini@ti.com Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| | * | board/BuR/common: Add CONFIG_CMD_I2CHannes Petermaier2014-06-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in almost all cases we need the i2c commands within the u-boot shell. So we enable them within the common section. Cc: trini@ti.com Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| | * | board/BuR/tseries: only run gpmc_init(...) in NAND-buildHannes Petermaier2014-06-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if we have no NAND-Chip, we don't need the gpmc-controller and therefore is no need to init it. Cc: trini@ti.com Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| | * | board/BuR/tseries: Add support for using 8-bit on eMMCHannes Petermaier2014-06-06-0/+5
| | | | | | | | | | | | | | | | | | | | Cc: trini@ti.com Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| | * | board/BuR/common: introduce usage of CONFIG_SYS_GENERIC_BOARDHannes Petermaier2014-06-06-0/+2
| | | | | | | | | | | | | | | | Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| | * | arch-am33xx: Add defines for timer0-7Hannes Petermaier2014-06-06-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For usage of timer6 within B&R we need this defines to enable clock modules and clk-source. Also the 'Timer register bits' are expanded. By the way we add defines for all timers within AM335x SoC. Cc: trini@ti.com Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| | * | ARM: AM43xx: Fix UART clocks enablingLokesh Vutla2014-06-06-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After enabling a module, SW has to wait on IDLEST bit until it is Fully functional. This wait is missing for UART module and there is a immediate access of UART registers after this. So there is a chance of hang on this module( This can happen when we are running from MPU SRAM). So waiting for IDLEST bit. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * | ARM: AM43xx: Fix mmcboot command in EXTRA_ENV_SETTINGSLokesh Vutla2014-06-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | loadbootenv expects devtype variable to be set. This is missing in mmcboot command. With this the following error comes: U-Boot# run mmcboot mmc0 is current device SD/MMC found on device 0 ** Bad device usb 0 ** ** Bad device usb 0 ** Fixing this by setting devtype as mmc. Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| | * | tam3517: fix NAND detectionJeroen Hofstee2014-06-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit a0a37183bd7 "ARM: omap: merge GPMC initialization code for all platform" needs CONFIG_NOR, CONFIG_NAND or CONFIG_CMD_ONENAND to be set to access flash. Add CONFIG_NAND for tam3517 derived boards to prevent the following error: "nand: error: Unable to find NAND settings in GPMC Configuration - quitting" cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| | * | keystone: k2hk: enable support of nand ecclayout commandWingMan Kwok2014-06-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support of nand ecclayout command. Acked-By: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | keystone: init: enable UART1 to be able use it from kernelMurali Karicheri2014-06-06-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PWREMU_MGMT is not configured in the Linux generic UART driver as this register seems to be specific TI UART IP. So this needs to be enabled in u-boot to use UART1 from kernel space. Acked-By: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| | * | arm:am33xx: Rework s_init and add board_early_init_fTom Rini2014-06-06-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the changes to the i2c framework (and adopting the omap24xx_i2c driver to them) we can no longer call i2c functions prior to gd having been set and cleared. When SPL booting, this is handled by setting gd to point to SRAM in s_init. However in the cases where we are loaded directly by ROM (memory mapped NOR or QSPI) we need to make use of the normal hooks to slightly delay these calls. Signed-off-by: Tom Rini <trini@ti.com>
| | * | arm:am33xx: Make dram_init call sdram_init() in some contextsTom Rini2014-06-06-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have two contexts for booting these platforms. One is SPL which is roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main, board_init_f from SPL, ... then U-Boot loads. The other is a memory-mapped XIP case (NOR or QSPI) where we do not run an SPL. In this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init, _main, regular board_init_f. In the first case s_init will set a valid gd and then be able to call sdram_init which in many cases will need i2c (which needs a valid gd for gd->cur_i2c_bus). In this second case we must (and are able to and should) defer sdram_init() into dram_init() called by board_init_f as gd will have been set in _main and cleared in board_init_f. Signed-off-by: Tom Rini <trini@ti.com>
| | * | ti: qspi: populate slave device to set flash quad bit.Sourav Poddar2014-06-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch populates the slave data which will be used by flash driver to set the flash quad enable bit. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
| | * | am43xx_evm: Add qspiboot targetSourav Poddar2014-06-06-7/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot target that utilizes QSPI for env and so forth as an example of best practices. As QSPI is booted from directly we need to chang CONFIG_SYS_TEXT_BASE. Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices we need to handle that elsewhere, once NAND support is also added. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
| | * | am335x: update README for BCH16pekon gupta2014-06-06-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | updates documentation with explanation on how to select ECC schemes. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: omap: add support for BCH16_ECC - NAND driver updatespekon gupta2014-06-06-1/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support for BCH16_ECC to omap_gpmc driver. *need to BCH16 ECC scheme* With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes Flash devices have become more suspectible to bit-flips. Thus stronger ECC schemes are required for protecting the data. But stronger ECC schemes have come with larger-sized ECC syndromes which require more space in OOB/Spare. This puts constrains like; (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data. (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page >= 26 * (page-size / 512) Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: omap_gpmc: use macro for register definitionspekon gupta2014-06-06-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and ↵pekon gupta2014-06-06-31/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC_NAND_ECC_LP_x16_LAYOUT OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros to configure GPMC controller for x7 or x8 bit device connected to its interface. Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above macros can be completely removed. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: omap: add CONFIG_SYS_NAND_BUSWIDTH_16BIT to indicate NAND device ↵pekon gupta2014-06-06-5/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bus-width GPMC controller needs to be configured based on bus-width of the NAND device connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI parameters is not possible in following situations: SPL: SPL NAND drivers does not support ONFI parameter reading. U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init() which is called before probing for devices, hence any ONFI parameter information is not available during GPMC initialization. Thus, OMAP NAND driver expected board developers to explicitely write GPMC configurations specific to NAND device attached on board in board files itself. But this was troublesome for board manufacturers as they need to dive into lengthy platform & SoC documents to find details of GPMC registers and appropriate configurations to get NAND device working. This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config hich indicates that connected NAND device has x16 bus-width. And then based on this config GPMC driver itself initializes itself based on NAND bus-width. This keeps board developers free from knowing GPMC controller specific internals. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: fix GET/SET_FEATURES address on 16-bit devicesDavid Mosberger2014-06-06-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per following Sections in ONFI Spec, GET_FEATURES and SET_FEATURES also need byte-addressing on 16-bit devices. *Section: Target Initialization" "The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page." *Section: Bus Width Requirements* "When the host supports a 16-bit bus width, only data is transferred at the 16-bit width. All address and command line transfers shall use only the lower 8-bits of the data bus. During command transfers, the host may place any value on the upper 8-bits of the data bus. During address transfers, the host shall set the upper 8-bits of the data bus to 00h." So porting following commit from linux kernel commit e34fcb07a6d57411de6e15a47724fbe92c5caa42 Author: David Mosberger <davidm@egauge.net> (preserving authorship) mtd: nand: fix GET/SET_FEATURES address on 16-bit devices Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: force NAND_CMD_READID onto 8-bit busBrian Norris2014-06-06-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per following Sections in ONFI Spec, NAND_CMD_READID should use only lower 8-bit for transfering command, address and data even on x16 NAND device. *Section: Target Initialization" "The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page." *Section: Bus Width Requirements* "When the host supports a 16-bit bus width, only data is transferred at the 16-bit width. All address and command line transfers shall use only the lower 8-bits of the data bus. During command transfers, the host may place any value on the upper 8-bits of the data bus. During address transfers, the host shall set the upper 8-bits of the data bus to 00h." Thus porting following commit from linux-kernel to ensure that column address is not altered to align to x16 bus when issuing NAND_CMD_READID command. commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7 mtd: nand: force NAND_CMD_READID onto 8-bit bus Author: Brian Norris <computersforpeace@gmail.com> (preserving authorship) The NAND command helpers tend to automatically shift the column address for x16 bus devices, since most commands expect a word address, not a byte address. The Read ID command, however, expects an 8-bit address (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or 0x20). This fixes the column address for a few drivers which imitate the nand_base defaults. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: don't use read_buf for 8-bit ONFI transfersBrian Norris2014-06-06-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Porting below commit from linux-tree, preserving original authorship & commit log commit bd9c6e99b58255b9de1982711ac9487c9a2f18be Author: Brian Norris <computersforpeace@gmail.com> mtd: nand: don't use read_buf for 8-bit ONFI transfers Use a repeated read_byte() instead of read_buf(), since for x16 buswidth devices, we need to avoid the upper I/O[16:9] bits. See the following commit for reference: commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree) Author: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Date: Thu Dec 5 22:22:04 2013 +0100 mtd: nand: don't use {read,write}_buf for 8-bit transfers Now, I think that all barriers to probing ONFI on x16 devices are removed, so remove the check from nand_flash_detect_onfi(). Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: omap: fix error-codes returned from omap-elm driverpekon gupta2014-06-06-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch omap-elm.c: replaces -ve integer value returned during errorneous condition, with proper error-codes. omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from omap-elm driver to upper layers Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
| | * | mtd: nand: omap_gpmc: minor cleanup of omap_correct_data_bchpekon gupta2014-06-06-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch tries to avoid some local pointer dereferences, by using common local variables in omap_correct_data_bch() Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
| | * | mtd: nand: omap_gpmc: rename struct nand_bch_priv to struct omap_nand_infopekon gupta2014-06-06-32/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch renames 'struct nand_bch_priv' which currently holds private data only for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for all ECC schemes Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
| | * | mtd: nand: omap_gpmc: remove unused members of 'struct nand_bch_priv'pekon gupta2014-06-06-17/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info' And thus performs following clean-ups: - remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead - remove nand_bch_priv.mode: <unused> Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
| | * | mtd: nand: omap_elm: use macros for register definitionspekon gupta2014-06-06-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds macros for following parameters of ELM Hardware engine - ELM_MAX_CHANNELS: ELM can process 8 data streams simultaneously - ELM_MAX_ERRORS: ELM can detect upto 16 ECC error when using BCH16 scheme Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
| | * | mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate ↵pekon gupta2014-06-06-21/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | between BCH4/BCH8/BCH16 ELM hardware engine support ECC error detection for multiple ECC strengths like +------+------------------------+ |Type | ECC syndrome length | +------+------------------------+ |BCH4 | 6.5 bytes = 13 nibbles | |BCH8 | 13 byte = 26 nibbles | |BCH16 | 26 bytes = 52 nibbles | +------+------------------------+ Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles') to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type' Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
| | * | mtd: nand: omap_elm: remove #include omap_gpmc.hpekon gupta2014-06-06-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no dependency of omap_elm.c on omap_gpmc.h Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-10-30 22:20:26 +0000