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* rockchip: add boot-mode support for rk3288, rk3036Jacob Chen2016-10-01-20/+111
| | | | | | | | | | | | rockchip platform have a protocol to pass the the kernel reboot mode to bootloader by some special registers when system reboot. In bootloader we should read it and take action. We can only setup boot_mode in board_late_init becasue "setenv" need env setuped. So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init" to replace "board_late_init" in board file. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: move common function from board-file to rk3036-board.cJacob Chen2016-10-01-132/+84
| | | | | | | To keep it same with 3288 Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rename board.c to rk3288-board.cJacob Chen2016-10-01-1/+1
| | | | | Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: move partitons define from 3036-kylin to 3036-commonJacob Chen2016-10-01-24/+10
| | | | | | | To keep it same with 3288. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: miniarm: remove eMMC supportXu Ziyuan2016-10-01-21/+6
| | | | | | | The latest rk3288-miniarm board doesn't have eMMC device, so remove it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* config: evb-rk3399: enable pwm regulatorKever Yang2016-10-01-0/+1
| | | | | | | Enable the pwm regulator for evb-rk3399. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* dts: evb-rk3399: add init voltage node for vdd-centerKever Yang2016-10-01-0/+1
| | | | | | | | | | | Add a regulator-init-microvolt for vdd_center regulator so that we can get a init value for driver probe. Not like pmic regulator, the PWM regulator do not have a known default output value, so we would like to init the regulator when driver probe. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* Kconfig: rockchip: enable DM_PWM and DM_REGULATORKever Yang2016-10-01-0/+2
| | | | | | | Enable DM_PWM and DM_REGULATOR on rockchip SoCs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: evb_rk3399: init vdd_center regulatorKever Yang2016-10-01-0/+6
| | | | | | | | Add vdd_center pwm regulator get_device to enable this regulator. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* power: regulator: add pwm regulatorKever Yang2016-10-01-0/+170
| | | | | | | | add driver support for pwm regulator. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rkpwm: fix the register sequenceKever Yang2016-10-01-1/+1
| | | | | | | | | Reference to kernel source code, rockchip pwm has three type, we are using v2 for rk3288 and rk3399, so let's update the register to sync with pwm_data_v2 in kernel. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3399: update PPLL and pmu_pclk frequencyKever Yang2016-10-01-2/+2
| | | | | | | | | | | | | | Update PPLL to 676MHz and PMU_PCLK to 48MHz, because: 1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz can not, 2. We think 48MHz is fast enough for pmu pclk and it is lower power cost than 99MHz, 3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using internally for kernel,it suppose not to change the bus clock like pmu_pclk in kernel, so we want to change it in uboot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add usb mass storage feature support for rk3036jacob2.chen2016-10-01-0/+4
| | | | | | | | Enable ums feature for rk3036 boards, so that we can mount the mmc device to PC. Signed-off-by: jacob2.chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* Enable ROCKCHIP_SPL_BACK_TO_BROM for rock2 boardSandy Patterson2016-10-01-0/+11
| | | | | | | | | | | | Rock2 has been tested with back to brom feature. The tricky part is that with this feature the default environment is inside u-boot, and it's defined for every rk3288 board independetly. So I just changed it for rock2 here if ROCKCHIP_SPL_BACK_TO_BROM. Solve by moving environment after u-boot before 1M boundary Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Simon Glass <sjg@chromium.org>
* Disable SPL_MMC_SUPPORT if ROCKCHIP_SPL_BACK_TO_BROM is enabled.Sandy Patterson2016-10-01-0/+3
| | | | | | | | Default SPL_MMC_SUPPORT to false when ROCKCHIP_SPL_BACK_TO_BROM is enabled. Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Fix SPL console output when ROCKCHIP_SPL_BACK_TO_BROM is enabledSandy Patterson2016-10-01-1/+4
| | | | | | | | | | | | | | | | | Move back_to_bootrom() call later in SPL init so that the console is initialized and printouts happen. Currently when ROCKCHIP_SPL_BACK_TO_BROM is enabled there is no console output from the SPL init stages. I wasn't sure exactly where this should happen, so if we are set to do run spl_board_init, then go back to bootrom there after preloader_console_init(). Otherwise fall back to old behavior of doing it in board_init_f. Signed-off-by: Sandy Patterson <apatterson@sightlogix.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: sdram: fix DDR address rangeXu Ziyuan2016-10-01-3/+4
| | | | | | | | | | | | | | | | The all current Rockchip SoCs supporting 4GB of ram have problems accessing the memory region 0xfe000000~0xff000000. Actually, some IP controller can't address to, so let's limit the available range. This patch fixes a bug which found in miniarm-rk3288-4GB board. The U-Boot was relocated to 0xfef72000, and .bss variants was also relocated, such as do_fat_read_at_block. Once eMMC controller transfer data to do_fat_read_at_block via DMA, DMAC can't access more than 0xfe000000. So that DMAC didn't work sane. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-nds32Tom Rini2016-09-30-74/+77
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| * nds32: Support relocation.rick2016-09-29-74/+77
| | | | | | | | | | | | | | Enable pie option for relocation. Signed-off-by: rick <rick@andestech.com> Cc: Andes <uboot@andestech.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-09-30-156/+574
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/dra7xx_evm.h
| * | drivers: usb: xhci-fsl: Implement Erratum A-010151 for FSL USB3 controllerSriram Dash2016-09-27-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the controller by default enables the Receive Detect feature in P3 mode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive detection in P3 mode. Enabling the USB3 controller to configure USB in P2 mode whenever the Receive Detect feature is required. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * | usb: fsl: Renaming fdt_fixup_erratum and fdt_fixup_usb_erratumSriram Dash2016-09-27-22/+23
| | | | | | | | | | | | | | | | | | | | | | | | The functions fdt_fixup_erratum and fdt_fixup_usb_erratum are fsl/nxp specific. So, make them explicit by renaming them fsl_fdt_fixup_erratum and fsl_fdt_fixup_usb_erratum Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
| * | usb: fsl: Rename fdt_fixup_dr_usbSriram Dash2016-09-27-36/+36
| | | | | | | | | | | | | | | | | | | | | | | | The function fdt_fixup_dr_usb is specific to fsl/nxp. So, make the function name explicit and rename fdt_fixup_dr_usb into fsl_fdt_fixup_dr_usb. Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
| * | apalis_t30: colibri_imx7: colibri_t30: fix ethernet functionalityMarcel Ziswiler2016-09-27-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit aa7a648747d8c704a9a81c9e493d386930724e9d ("net: Stop including NFS overhead in defragment max") the following has been reproducibly observed while trying to transfer data over TFTP: Load address: 0x80408000 Loading: EHCI timed out on TD - token=0x8008d80 T EHCI timed out on TD - token=0x88008d80 Rx: failed to receive: -5 This patch fixes this by lowering our TFTP block size to be within the standard maximal de-fragmentation aka IP packet size again. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| * | configs: colibri_vf_defconfig: Enable USB driver model for Colibri VybridSanchayan Maity2016-09-27-0/+1
| | | | | | | | | | | | | | | | | | Enable USB driver model for Toradex Colibri Vybrid modules. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | ARM: dts: vf-colibri: Enable USB device tree node for Colibri VybridSanchayan Maity2016-09-27-0/+11
| | | | | | | | | | | | | | | | | | Enable USB device tree node for Toradex Colibri Vybrid module. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | ARM: dts: vf: Add device tree node for USB on VybridSanchayan Maity2016-09-27-0/+14
| | | | | | | | | | | | | | | | | | Add device tree node for USB peripheral on Vybrid. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | usb: host: ehci-vf: Migrate Vybrid USB to driver modelSanchayan Maity2016-09-27-7/+201
| | | | | | | | | | | | | | | | | | Add driver model support for Vybrid USB driver. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | cmd: dfu: Add error handling for failed registrationSanchayan Maity2016-09-27-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Without this, if g_dnl_register() fails, DFU code continues on blindly and crashes. This fix makes it simply print an error message instead. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> [l.majewski@samsung.com - some manual tweaks needed]
| * | dra7x: configs: enable SPL-DFU supportB, Ravi2016-09-27-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | This patch enables the SPL-DFU support for dra7x platform. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | dra7x: boot: add dfu bootmode supportB, Ravi2016-09-27-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | This patch enables the DFU boot mode support for dra7x platform. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | spl: dfu: adding dfu support functions for SPL-DFUB, Ravi2016-09-27-0/+66
| | | | | | | | | | | | | | | | | | | | | Adding support functions to run dfu spl commands. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | common: dfu: saperate the dfu common functionalityB, Ravi2016-09-27-59/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | The cmd_dfu functionality is been used by both SPL and u-boot, saperating the core dfu functionality moving it to common/dfu.c. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | spl: dfu: add dfu support in SPLB, Ravi2016-09-27-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Traditionally the DFU support is available only as part 2nd stage boot loader(u-boot) and DFU is not supported in SPL. The SPL-DFU feature is useful for boards which does not have MMC/SD, ethernet boot mechanism to boot the board and only has USB inteface. This patch add DFU support in SPL with RAM memory device support to load and execute u-boot. And then leverage full functionality DFU in u-boot to flash boot inital binary images to factory or bare-metal boards to memory devices like SPI, eMMC, MMC/SD card using USB interface. This SPL-DFU support can be enabled through Menuconfig->Boot Images->Enable SPL-DFU support Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | drivers: usb: xhci-fsl: Change burst beat and outstanding pipelined ↵Sriram Dash2016-09-27-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | transfers requests This is required for better performance, and performs below tuning: 1. Enable burst length set, and define it as 4/8/16. 2. Set burst request limit to 16 requests. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
| * | colibri_t30: fix usb ethernet functionalityMarcel Ziswiler2016-09-27-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit aa7a648747d8c704a9a81c9e493d386930724e9d ("net: Stop including NFS overhead in defragment max") the following has been reproducibly observed while trying to transfer data over TFTP: Load address: 0x80408000 Loading: EHCI timed out on TD - token=0x8008d80 T EHCI timed out on TD - token=0x88008d80 Rx: failed to receive: -5 This patch fixes this by upping our maximal de-fragmentation aka IP packet size again. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| * | net: asix: Fix ASIX 88772B with driver modelAlban Bedel2016-09-27-24/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 147271209a9d ("net: asix: fix operation without eeprom") added a special handling for ASIX 88772B that enable another type of header. This break the driver in DM mode as the extra handling needed in the receive path is missing. However this new header mode is not required and only seems to increase the code complexity, so this patch revert this part of commit 147271209a9d. This also reverts commit 41d1258aceb45b45f9e68f67a9c40f0afbc09dc9 ("net: asix: Fix AX88772B when used with DriverModel") of late. Fixes: 147271209a9d ("net: asix: fix operation without eeprom") Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* | | mpc85xx: powerpc: usb: Update the list of Socs afftected by erratum A006261Sriram Dash2016-09-28-12/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apply the erratum A006261 for the following Socs: P2041 rev 2.0, P2040 rev 2.0, P5040 rev 2.0, 2.1 Do not apply erratum A006261 for the following Socs: T4160, T4080, T1040, T1042, T1020, T1022, T2080, T2081 Erratum A006261 is applicable for the following Socs: P1010(1.0, 2.0), P2041(1.0, 1.1, 2.0, 2.1), P2040(1.0, 1.1, 2.0, 2.1), P3041(1.0, 1.1, 2.0, 2.1), P5010(1.0, 2.0), P5020(1.0, 2.0), P5021(1.0, 2.0), T4240(1.0, 2.0), P5040(1.0,2.0,2.1). Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010Sriram Dash2016-09-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | mpc85xx: powerpc: usb: Modified the erratum A006261 according to endiannessSriram Dash2016-09-28-2/+2
| |/ |/| | | | | | | | | | | | | | | | | Modifies erratum implementation due to the fact that P3041, P5020, and P5040 are all big endian for the USB PHY registers, but they were specified little endian. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge git://www.denx.de/git/u-boot-ppc4xxTom Rini2016-09-27-7/+0
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| * | CPCI4052: Remove CONFIG_AUTO_COMPLETE and custom baud rate tableTom Rini2016-09-27-7/+0
| |/ | | | | | | | | | | | | | | | | | | This board is getting close to or exceeding the size limit again, remove CONFIG_AUTO_COMPLETE to save space and while in here switch to the default and slightly less complete default baudrate table. Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-09-27-1235/+3555
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| * | ARM: tegra: flush caches via SMC callStephen Warren2016-09-27-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra186, it is necessary to perform an SMC to fully flush all caches; flushing/cleaning by set/way is not enough. Implement the required hook to make this happen. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: fix ULPI PHY on Ventana and SeaboardStephen Warren2016-09-27-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ce02a71c2374 "tegra: dts: Sync tegra20 device tree files with Linux" enabled the ULPI USB port on Ventana, but made no attempt to ensure that U-Boot code could handle this. In practice, various code is missing, and various configuration options are not enabled, which causes U-Boot to hang when attempting to initialize this USB port. This patch enables ULPI PHY support on Ventana, and adds the required pinmux setup for the port to operate. Note that Ventana is so similar to Seaboard that this change is made in the Seaboard board file, which is shared with Ventana. Seaboard also has the ULPI USB port wired up in hardware, although to an internal port that often doesn't have anything attached to it. However, the DT nodes for the USB controller and PHY had different status property values, so the port was not initialized by U-Boot. Fix this inconsistency, and enable the ULPI port, just like in the Linux kernel DT. This likewise requires enabling ULPI support in the Seaboard defconfig. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: fix USB controller aliasesStephen Warren2016-09-27-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards have a different set of USB controllers enabled in DT than the set referenced by /alias entries. This patch fixes that. For example, this avoids the following message while booting on Ventana, which is caused by the fact that the USB0 controller had no alias, and defaulted to wanting a sequence number of 0, which was later explicitly requested by the alias for USB controller 2. USB2: Device 'usb@c5008000': seq 0 is in use by 'usb@c5000000' This didn't affect USB operation in any way though. Related, there's no need for the USB controller aliases to have an order that's different from the HW order, so re-order any aliases to match the HW ordering. This has the benefit that since USB controller 0 is the only one that supports device-mode in HW, and U-Boot only supports enabling device move on controller 0, there's now good synergy in the ordering! For Tegra20, that's not relevant at present since USB device mode doesn't work correctly on that SoC, but it will save some head-scratching later. This patch doesn't fix the colibri_t20 board, even though it has the same issue, since Marcel already sent a patch for that. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Harmony and Ventana
| * | ARM: tegra: fix USB ULPI PHY reset signal inversion confusionStephen Warren2016-09-27-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB ULPI PHY reset signals are typically active low. Consequently, they should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use. However, in DT properties that U-Boot does use, the value has been set to 0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot. This change fixes the DT to correctly represent the HW, and fixes the Tegra USB driver to cope with the fact that dm_gpio_set_value() internally handles any inversions implied by the DT value GPIO_ACTIVE_LOW. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | i2c: tegra: only use new clock/reset APIsStephen Warren2016-09-27-57/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the standard clock/reset APIs are available for all Tegra SoCs, convert the I2C driver to use them exclusively, and remove any references to the custom Tegra-specific APIs. Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | mmc: tegra: only use new clock/reset APIsStephen Warren2016-09-27-40/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the standard clock/reset APIs are available for all Tegra SoCs, convert the MMC driver to use them exclusively, and remove any references to the custom Tegra-specific APIs. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: enable standard clock/reset APIs everywhereStephen Warren2016-09-27-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implementations of the standard clock and reset APIs are available on all Tegra SoCs now, so enable compilation of those uclasses. Enable the Tegra CAR drivers for all SoCs prior to the BPMP being available. This provides an implementation of those APIs everywhere. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>