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* eeprom: fix eeprom write procedureAlexey Brodkin2015-12-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This fixes commit 1a37889b0ad084a740b4f785031d7ae9955d947b: ----------------------->8-------------------- eeprom: Pull out the RW loop Unify the code for doing read/write into single function, since the code for both the read and write is almost identical. This again trims down the code duplication. ----------------------->8-------------------- where the same one routine is utilized for both EEPROM writing and reading. The only difference was supposed to be a "read" flag which in both cases was set with 1 somehow. That lead to a missing delay in case of writing which lead to write failure (in my case no data was written). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Heiko Schocher <hs@denx.de>
* Revert "include/linux: move typdef for uintptr_t"York Sun2015-12-16-1/+3
| | | | | | | | This reverts commit e8f954a756a825130d11b9c8fca70101dd8b3ac5, which causes compiling errors on 32-bit hosts. Acked-by: Aneesh Bansal <aneesh.bansal@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-12-14-283/+1079
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| * armv8: Add sata support on Layerscape ARMv8 boardTang Yuantian2015-12-15-0/+131
| | | | | | | | | | | | | | | | | | | | | | Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/crypto/fsl: fix endianness issue in RNGAneesh Bansal2015-12-15-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For Setting and clearing the bits in SEC Block registers sec_clrbits32() and sec_setbits32() are used which work as per endianness of CAAM block. So these must be used with SEC register address as argument. If the value is read in a local variable, then the functions will not behave correctly where endianness of CAAM and core is different. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> CC: Alex Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal2015-12-15-21/+82
| | | | | | | | | | | | | | | | | | | | LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * include/linux: move typdef for uintptr_tAneesh Bansal2015-12-15-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address. If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit. The typdef has been moved from include/compiler.h to include/linux/types.h Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8: Make SEC read/write as snoopable for LS1043Aneesh Bansal2015-12-15-0/+5
| | | | | | | | | | | | | | | | For LS1043, SEC read/writes are made snoopable by setting the corresponding bits in SCFG to avoid coherency issues. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8: define usec2ticks functionAneesh Bansal2015-12-15-0/+11
| | | | | | | | | | | | | | | | usec2ticks() function has been defined for ARMv8 which will be used by SEC Driver. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_qspi: Pet the watchdog while reading/writingAlexander Stein2015-12-15-0/+5
| | | | | | | | | | | | | | | | | | When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog timeout might occur meanwhile. So pet the watchdog while operating on the flash. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8: fsl-layerscale: Rewrite reserving memory for MC and debug serverYork Sun2015-12-15-60/+25
| | | | | | | | | | | | | | | | | | | | | | MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com>
| * common: Rewrite hiding the end of memoryYork Sun2015-12-15-9/+16
| | | | | | | | | | | | | | | | | | | | | | As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves some memory from the end of ram, tracked by gd->ram_size. It is not always the top of u-boot visible memory. Rewrite the macro with a weak function to provide flexibility for complex calcuation. Legacy use of this macro is still supported. Signed-off-by: York Sun <yorksun@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * armv8: fsl-layerscape: Make DDR non secure in MMU tablesYork Sun2015-12-15-19/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
| * Reserve secure memoryYork Sun2015-12-15-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secure memory is at the end of memory, separated and reserved from OS, tracked by gd->secure_ram. Secure memory can host MMU tables, security monitor, etc. This is different from PRAM used to reserve private memory. PRAM offers memory at the top of u-boot memory, not necessarily the real end of memory for systems with very large DDR. Using the end of memory simplifies MMU setup and avoid memory fragmentation. "bdinfo" command shows gd->secure_ram value if this memory is marked as secured. Signed-off-by: York Sun <yorksun@freescale.com>
| * move erratum a008336 and a008514 to soc specific fileYao Yuan2015-12-15-34/+37
| | | | | | | | | | | | | | | | As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/fsl-ls102xa: Workaround for DDR erratum A008514Yao Yuan2015-12-15-1/+11
| | | | | | | | | | | | | | | | | | | | | | This is a workaround for hardware erratum. Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance. The value: 63b2_0042h comes from the hardware team. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7: ls102xa: cci-400: Enable snoop and DVM message requests.Yao Yuan2015-12-15-1/+7
| | | | | | | | | | | | | | | | | | Enable snoop and DVM message on all CCI-400 slave ports. Setting on disabled feature (snoop or DVM) is ignored by CCI-400. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> [York Sun: Add commit message] Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: enable all the snoop signal for masters.Yao Yuan2015-12-13-0/+14
| | | | | | | | | | | | | | | | | | | | | | Enable the IP feature's snoop signal to support hardware snoop for cache coherence. SNPCNFGCR contains the bits to drive snoop signal for various masters. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls1021a: merge SoC specific code in a separate fileYao Yuan2015-12-13-87/+83
| | | | | | | | | | | | | | Create a soc.c file to put the code for soc special settings. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * qbman_portal.c: Update BUG_ON() call in qbman_swp_mc_submitTom Rini2015-12-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With gcc-5.x we get a warning about the ambiguity of BUG_ON(!a != b) and becomes BUG_ON((!a) != b). In this case reading of the function leads to us wanting to rewrite this as BUG_ON(a != b). Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Geoff Thorpe <Geoff.Thorpe@freescale.com> Cc: Haiying Wang <Haiying.Wang@freescale.com> Cc: Roy Pledge <Roy.Pledge@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl_*_serdes.c: Modify memset call in serdes_initTom Rini2015-12-13-3/+3
| | | | | | | | | | | | | | | | | | | | | | GCC 5.x does not like sizeof(array_variable) and errors out. Change these calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) * SERDES_PRCTL_COUNT (the number of array elements). Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * Enable console log from earlyconsole in Linux bootargsPratiyush Mohan Srivastava2015-12-13-2/+2
| | | | | | | | | | | | | | | | Remove 115200 from "earlycon" to avoid loss of initial log messages during linux kernel 4.1 bootup Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add support for >2GB memoryShaohui Xie2015-12-13-4/+22
| | | | | | | | | | | | | | | | This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu2015-12-13-3/+39
| | | | | | | | | | | | | | | | | | DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl/errata: move fsl_errata.h to common directoryShengzhou Liu2015-12-13-7/+15
| | | | | | | | | | | | | | | | | | move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102x: add get_svr and IS_SVR_REV helperShengzhou Liu2015-12-13-0/+13
| | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * freescale: fman: make sure phy-handle property is big endianShaohui Xie2015-12-13-0/+2
| | | | | | | | | | | | | | | | | | | | When creating phy-handle property, an unsigned int value is created by fdt_create_phandle, and memcpy is used to get the value, since DTS is big endian, the value cannot be used directly on little endian SoCs, it should be converted by cpu_to_fdt32. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2080ardb: Update DDR settings for four chip-select caseYork Sun2015-12-13-4/+12
| | | | | | | | | | | | | | When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/ls2080aqds: Update DDR settings for four chip-select caseYork Sun2015-12-13-4/+12
| | | | | | | | | | | | | | When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Update timing config for heavy loadYork Sun2015-12-13-2/+24
| | | | | | | | | | | | | | In case four chip-selects are all active, the turnaround times need to increase to avoid overlapping under heavy load. Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Update workaround for A008511 for vref rangeYork Sun2015-12-13-7/+15
| | | | | | | | | | | | | | The workaround requires different setting for range 1 vs 2. Also adjust timeout value for waiting for controller to be idle. Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Update MR5 RTT parkYork Sun2015-12-13-4/+15
| | | | | | | | | | | | For four chip-selects enabled case, RTT is parked on all of them. Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Update DDR4 MR6 for Vref rangeYork Sun2015-12-13-0/+3
| | | | | | | | | | | | MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec. Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Update DDR4 RTT valuesYork Sun2015-12-13-2/+244
| | | | | | | | | | | | | | DDR4 has different RTT value and code according to JEDEC spec. Update the macros and options . Signed-off-by: York Sun <yorksun@freescale.com>
* | armv7: omap-common: Rework SPL board_mmc_init()Tom Rini2015-12-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the changes in a1e56cf the way that we had board_mmc_init() structured for OMAP parts (so that we always report device 0) are no longer functional. For now, make the case of booting from the second device initialize both devices (we have no devices that only have the second device as MMC). A further rework and consolidation of the functions should be done at a later date. Tested on Beaglebone Black (SD and eMMC boot). Reported-by: Vagrant Cascadian <vagrant@debian.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | spl: mmc: use block device number, not hard-coded 0Eric Nelson2015-12-14-3/+5
| | | | | | | | | | | | | | | | | | | | | | In order to support boot from multiple devices through board_boot_order, it's necessary to use the block number of a device. The use of a hard-coded 0 for the device number also creates a need to re-order block devices for use in SPL like this: http://git.denx.de/?p=u-boot.git;a=blob;f=board/freescale/mx6slevk/mx6slevk.c;hb=HEAD#l195 Signed-off-by: Eric Nelson <eric@nelint.com>
* | part: fix "part list ... -bootable varname" to use hexStephen Warren2015-12-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately U-Boot assumes that almost all numbers are in hex, including partition numbers passed to e.g. "load". So, the command "part list mmc 0 -bootable devplist" should use hex when writing partition numbers into $devplist, so they'll be correctly interpreted. Change-Id: I9a70b19749643876baadb45efbc3decaef8bfee2 Fixes: 0798d6fd4191 ("part: Add support for list filtering on bootable partitions") Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
* | tools: env: include compiler.hPeter Robinson2015-12-13-0/+1
| | | | | | | | | | | | | | With gcc 5.2 and later we get a bunch of "error: unknown type name" for 'uint8_t', 'uint32_t' and friends. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
* | m68k: add private libgccangelo@sysam.it2015-12-13-0/+176
| | | | | | | | | | | | Add private libgcc Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* | common: cli_hush: Fix up simple typoNishanth Menon2015-12-12-2/+2
| | | | | | | | | | | | | | Correct the spelling for character.. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | siemens,am33x: remove ddr3 delay workaroundEgli, Samuel2015-12-12-5/+0
| | | | | | | | | | | | Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Heiko Schocher <hs@denx.de>
* | am33xx,ddr3: fix ddr3 sdram configurationEgli, Samuel2015-12-12-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the DDR3 initialization procedure in order to comply with DDR3 standard. A 500 us delay is specified between the DDR3 reset and clock enable signal. Until now, this delay was not respected. Some DDR3 chips don't bother but the bigger the RAM becomes the more likely it seems that this delay is needed. We observed that DRAM > 256 MB from the manufacturer Samsung have an issue when the specification is not respected. Changes: 1) Add a 1 ms wait for L3 timeout error trigger 2) Don't delay DDR3 initialization Bit 31 of emif_sdram_ref_ctrl shouldn't be set because his suppresses the initialization of DDR3 Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Reviewed-by: James Doublesin <doublesin@ti.com> Cc: Tom Rini <trini@konsulko.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Heiko Schocher <hs@denx.de>
* | VxWorks: fixup MAC address for VxWorksMiao Yan2015-12-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | VxWorks 7 kernels retrieve 'local-mac-addr' from dtb and use that for NIC MAC address. As a result, when booting the same kernel image on multiple boards, there will be address conflicts. So fixup MAC address when booting VxWorks 7 kernels Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | stm32: Convert serial driver to DMKamil Lulko2015-12-12-119/+136
|/ | | | | | Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-12-11-419/+465
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| * spi: xilinx: Add new compatible stringsMichal Simek2015-12-11-1/+2
| | | | | | | | | | | | | | | | | | Add xlnx,xps-spi-2.00.a/b which is compatible string listed in the Linux kernel. Remove origin one which has no real background. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * mailmap: Update Jagan Teki's name and email addressJagan Teki2015-12-11-1/+5
| | | | | | | | | | | | | | | | | | Used quite different name's and e-mail address, all of them mapped to standard name and e-mail address. Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Rename sf_ops.c to spi-flash.cJagan Teki2015-12-11-4/+5
| | | | | | | | | | | | | | | | | | Since all spi-flash core operations are moved into sf_ops.c then it's better to renamed as spi-flash.c Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Use static for file-scope functionsJagan Teki2015-12-11-5/+5
| | | | | | | | | | | | | | | | Used static for file-scope functions in sf_probe.c Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: sf_probe: Remove spi_slave pointer argumentJagan Teki2015-12-11-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since spi_slave is a spi pointer in spi_flash{} then assign spi_slave{} pointer to flash->spi and remove spi_slave pointer argument to - spi_flash_probe_slave - spi_flash_scan Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
generated by cgit v1.1 at 2024-12-24 03:36:48 +0000