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authorYao Yuan <yao.yuan@freescale.com>2015-12-05 14:59:13 +0800
committerYork Sun <yorksun@freescale.com>2015-12-15 08:57:32 +0800
commit6c4a1eba3fcc013f7d21cdb88098bdd3e7afa75b (patch)
tree7476f1c1c4ff8f69dd9d410eb4889a784fb3c6ef
parent0b8bc6314e1abc4379cc00f93f949257e0b1b196 (diff)
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armv7/fsl-ls102xa: Workaround for DDR erratum A008514
This is a workaround for hardware erratum. Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance. The value: 63b2_0042h comes from the hardware team. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
-rw-r--r--arch/arm/cpu/armv7/ls102xa/soc.c10
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h2
2 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 97ba6d5..79ae883 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -76,5 +76,15 @@ int arch_soc_init(void)
SCFG_SNPCNFGCR_DBG_RD_WR |
SCFG_SNPCNFGCR_EDMA_SNP);
+ /*
+ * Memory controller require a register write before being enabled.
+ * Affects: DDR
+ * Register: EDDRTQCFG
+ * Description: Memory controller performance is not optimal with
+ * default internal target queue register values.
+ * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
+ */
+ out_be32(&scfg->eddrtqcfg, 0x63b20042);
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 9317272..89339fe 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -230,7 +230,7 @@ struct ccsr_scfg {
u32 scfgrevcr;
u32 coresrencr;
u32 pex2pmrdsr;
- u32 ddrc1cr;
+ u32 eddrtqcfg;
u32 ddrc2cr;
u32 ddrc3cr;
u32 ddrc4cr;