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* warp: Add initial WaRP Board supportOtavio Salvador2015-02-23-0/+345
| | | | | | | | | | | | | | | | | | | | | | The WaRP Board is a Wearable Reference Plaform. The board features: - Freescale i.MX6 SoloLite processor with 512MB of RAM - Freescale FXOS8700CQ 6-axis Xtrinsic sensor - Freescale Kinetis KL16 MCU - Freescale Xtrinsic MMA955xL intelligent motion sensing platform The board implements a hybrid architecture to address the evolving needs of the wearables market. The platform consists of a main board and an example daughtercard with the ability to add additional daughtercards for different usage models. For more information about the project, visit: http://www.warpboard.org/ Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6sl: Extend USDHC SD2 pins to support 8-wire useOtavio Salvador2015-02-23-0/+5
| | | | | | This adds the DATA[4-7] and RST pin definitions. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mmc: fsl_esdhc: Add support to force VSELECT setOtavio Salvador2015-02-23-0/+5
| | | | | | | | | Some boards cannot do voltage negotiation but need to set the VSELECT bit forcely to ensure it to work at 1.8V. This commit adds CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT flag for this use. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mmc: fsl_esdhc: Add CMD11 support to switch to 1.8VOtavio Salvador2015-02-23-7/+25
| | | | | | | This adds support to switch to 1.8V in case CMD11 succeeds. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Marek Vasut <marex@denx.de>
* imx:mx6slevk implement power init boardPeng Fan2015-02-23-0/+42
| | | | | | | | | | | | | | | | | | | | Implement power_init_board and related I2C interface configuration. After adding this, uboot can successfully detect and configure pmic. " U-Boot 2015.01-00281-ge29eddf (Feb 12 2015 - 09:24:01) CPU: Freescale i.MX6SL rev1.0 at 396 MHz Reset cause: POR Board: MX6SLEVK I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx:mx6slevk add pmic and i2c configurationPeng Fan2015-02-23-0/+12
| | | | | | Add pmic and i2c configuration in board header file. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx:mx6sl add I2c pad settingsPeng Fan2015-02-23-0/+5
| | | | | | A few pad settings are I2C1 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* board: tbs2910: Gate clock when switching async clock muxesSoeren Moch2015-02-23-12/+16
| | | | | | | | | | | According to the i.MX6Q Reference Manual, clocks must be gated when switching input clocks of async clock muxes. So use clock gates. Avoid ldb_di0_ipu clock, because there is no clock gate for this signal. There have never been any complaints about problems with the old code, but the new approach is in line with the recommendations in the manual. Signed-off-by: Soeren Moch <smoch@web.de>
* nitrogen6x: set environment variable reset_causeEric Nelson2015-02-17-0/+1
| | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* ARM: i.MX: provide access to reset cause through get_imx_reset_cause()Eric Nelson2015-02-17-1/+11
| | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* ot1200: add eeprom command to non-SPL buildChristian Gmeiner2015-02-17-0/+10
| | | | | Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* cmd_eeprom: make it possible to define the used i2c busChristian Gmeiner2015-02-17-0/+9
| | | | | | | | | | | A SoC like the i.MX6 supports more then one i2c bus. In oder to be able to use the eeprom command add a new define to specify the i2c bus to use. If CONFIG_SYS_I2C_EEPROM_BUS is not defined there is no functional change, else a call to i2c_set_bus_num(..) is done before calling i2c_read(..) and i2c_write(..). Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* ARM: imx6 Add WDOG3 for i.MX6SXPeng Fan2015-02-17-0/+5
| | | | | | | There are three wdogs for i.MX 6SoloX. Add wdog3 support in function imx_set_wdog_powerdown. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ARM: imx6: disable bandgap self-bias after bootPeng Fan2015-02-17-0/+26
| | | | | | | | | | | The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-02-13-24918/+48479
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| * sunxi: configs/sunxi-common.h: Enable CONFIG_CMD_PARTHans de Goede2015-02-11-0/+3
| | | | | | | | | | | | | | | | | | The recent changes to config_distro_bootcmd.h require CONFIG_CMD_PART to be defined, as the default bootcmd not uses the "part" command. This fixes sunxi boards not booting with v2015.04-rc1. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * Add linux/compiler-gcc5.h to fix builds with gcc5Hans de Goede2015-02-11-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | Add linux/compiler-gcc5/h from the kernel sources at: commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b Author: Steven Noonan <steven@uplinklabs.net> Date: Sat Oct 25 15:09:42 2014 -0700 compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2015-02-10-272/+11497
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| | * x86: Use tab instead of space to indent in PCIE_ECAM_BASEBin Meng2015-02-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Space is used before 'default' in PCIE_ECAM_BASE in arch/x86/Kconfig so it looks misaligned. Replace the space with tab to indent. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * bootstage: Fix typos in the commentBin Meng2015-02-06-2/+2
| | | | | | | | | | | | | | | | | | | | | There are two typos in the comment block in bootstage.h, fix them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add Intel Galileo instructions in README.x86Bin Meng2015-02-06-4/+20
| | | | | | | | | | | | | | | | | | | | | Add some instructions about building U-Boot for Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add SD/MMC support to quark/galileoBin Meng2015-02-06-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add SPI support to quark/galileoBin Meng2015-02-06-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: pci: Add pci ids for Quark SoCBin Meng2015-02-06-0/+4
| | | | | | | | | | | | | | | | | | | | | Add pci ids for Intel Quark SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: galileo: Add GPIO supportBin Meng2015-02-06-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31), which is just the same one found in other x86 chipset. Since we programmed the GPIO register block base address, we should be able to enable the GPIO support on Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: quark: Initialize non-standard BARsBin Meng2015-02-06-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | Quark SoC has some non-standard BARs (excluding PCI standard BARs) which need be initialized with suggested values. This includes GPIO, WDT, RCBA, PCIe ECAM and some ACPI register block base addresses. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: quark: Call MRC in dram_init()Bin Meng2015-02-06-2/+122
| | | | | | | | | | | | | | | | | | | | | | | | Now that we have added Quark MRC codes, call MRC in dram_init() so that DRAM can be initialized on a Quark based board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dt-bindings: Add Intel Quark MRC bindingsBin Meng2015-02-06-0/+83
| | | | | | | | | | | | | | | | | | | | | Add standard dt-bindings macros to be used by Intel Quark MRC node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * fdtdec: Add compatible id and string for Intel Quark MRCBin Meng2015-02-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add COMPAT_INTEL_QRK_MRC and "intel,quark-mrc" so that fdtdec can decode Intel Quark MRC node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: quark: Enable the Memory Reference Code buildBin Meng2015-02-06-0/+1
| | | | | | | | | | | | | | | | | | | | | Turn on the Memory Reference code build in the quark Makefile. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: quark: Add System Memory Controller supportBin Meng2015-02-06-0/+3210
| | | | | | | | | | | | | | | | | | | | | The codes are actually doing the memory initialization stuff. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: quark: Add utility codes needed for MRCBin Meng2015-02-06-0/+2068
| | | | | | | | | | | | | | | | | | | | | Add various utility codes needed for Quark MRC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: quark: Add Memory Reference Code (MRC) main routinesBin Meng2015-02-06-0/+391
| | | | | | | | | | | | | | | | | | | | | Add the main routines for Quark Memory Reference Code (MRC). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: quark: Bypass TSC calibrationBin Meng2015-02-06-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | For some unknown reason, the TSC calibration via PIT does not work on Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ to 400 per Quark datasheet in the Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Allow overriding TSC_FREQ_IN_MHZBin Meng2015-02-06-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | We should allow the value of TSC_FREQ_IN_MHZ to be overridden by the one in arch/cpu/<xxx>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Enable the Intel quark/galileo buildBin Meng2015-02-06-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the Intel quark/galileo support avaiable in Kconfig and Makefile. With this patch, we can generate u-boot.rom for Intel galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add basic Intel Galileo board supportBin Meng2015-02-06-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add basic Intel Quark processor supportBin Meng2015-02-06-0/+295
| | | | | | | | | | | | | | | | | | | | | | | | Add minimum codes to support Intel Quark SoC. DRAM initialization is not ready yet so a hardcoded gd->ram_size is assigned. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: quark: Add Cache-As-RAM initializationBin Meng2015-02-06-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is initialized by hardware. eSRAM is the ideal place to be used for Cache-As-RAM (CAR) before system memory is available. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Define macros for pci configuration space accessBin Meng2015-02-06-7/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these macros can be used for pci configuration space access. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: quark: Add routines to access message bus registersBin Meng2015-02-06-0/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Quark SoC, some chipset commands are accomplished by utilizing the internal message network within the host bridge (D0:F0). Accesses to this network are accomplished by populating the message control register (MCR), Message Control Register eXtension (MCRX) and the message data register (MDR). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add header files for Intel Quark SoC definesBin Meng2015-02-06-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | device.h for integrated pci devices' bdf on Quark SoC and quark.h for various memory-mapped and i/o-mapped base addresses within SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Remove CONFIG_SATA_INTEL from x86-common.hBin Meng2015-02-06-1/+0
| | | | | | | | | | | | | | | | | | | | | CONFIG_SATA_INTEL is not referenced anywhere, so remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Add support for Intel Minnowboard MaxSimon Glass2015-02-06-7/+4036
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Add some documentation on how to port U-Boot on x86Simon Glass2015-02-06-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | Some information has been gleaned on tools and procedures for porting U-Boot to different x86 platforms. Add a few notes to start things off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Enable bootstage featuresSimon Glass2015-02-06-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Allow measuring of boot time using bootstage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| | * scsi: bootstage: Measure time taken to scan the busSimon Glass2015-02-06-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | On some hardware this time can be significant. Add bootstage support for measuring this. The result can be obtained using 'bootstage report' or passed on to the Linux via the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: spi: Support ValleyView in ICH SPI driverSimon Glass2015-02-06-20/+47
| | | | | | | | | | | | | | | | | | | | | | | | The base address is found in a different way and the protection bit is also in a different place. Otherwise it is very similar. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Allow a UART to be set up before the FSP is readySimon Glass2015-02-06-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since the FSP is a black box it helps to have some sort of debugging available to check its inputs. If the debug UART is in use, set it up after CAR is available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: Allow FSP Kconfig settings for all x86Simon Glass2015-02-06-38/+38
| | | | | | | | | | | | | | | | | | | | | | | | While queensbay is the first chip with these settings, others will want to use them too. Make them common. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-09 19:14:12 +0000