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| * | | | spi: add TI QSPI driverMatt Porter2013-10-07-0/+312
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a SPI master driver for the TI QSPI peripheral. - Added quad read support. - Added memory mapped support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: Add memory mapped read supportPoddar, Sourav2013-10-07-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qspi controller can have a memory mapped port which can be used for data read. Added support to enable memory mapped port read. This patch enables the following: - It enables exchange of memory map address between mtd and qspi through the introduction of "memory_map" flag. - Add support to communicate to the driver that memory mapped transfer is to be started through introduction of new flags like "SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END". This will enable the spi controller to do memory mapped configurations if required. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | armv7: hw_data: change clock divider setting.Poddar, Sourav2013-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock requirement for qspi clk is 192 Mhz. According to the below formulae, f dpll = f ref * 2 * m /(n + 1) clockoutx2_Hmn = f dpll / (hmn+ 1) fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | omap5: add qspi supportMatt Porter2013-10-07-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | | sf: probe: Add support for EN25S64Priyanka Jain2013-10-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for EON EN25S64 SPI flash. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | doc: SPI: Add status.txt for tracking SPI subsys statusJagannadha Sutradharudu Teki2013-10-07-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | doc/SPI/status.txt added to track the u-boot SPI subsystem status. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: Rename spi_flash filesJagannadha Sutradharudu Teki2013-10-07-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Renamed: spi_flash.c -> sf.c spi_flash_internal.h -> sf_internal.h spi_flash_ops.c -> sf_ops.c spi_flash_probe.c -> sf_probe.c Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | spi: spi cleanupsJagannadha Sutradharudu Teki2013-10-07-43/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Rearranged multi-line comment style. - Add tabs. - Add spaces. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: spi_flash cleanupsJagannadha Sutradharudu Teki2013-10-07-74/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More cleanups on spi_flash side: - Removed unneeded comments. - Rearranged macros in proper location. - Rearranged func declerations - Renamed few function names. - Added License headers. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: Remove spi_flash_do_alloc referencesJagannadha Sutradharudu Teki2013-10-07-38/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added a support for common probe, hence removed removed spi_flash_do_alloc reference. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for MX25L51235FJagannadha Sutradharudu Teki2013-10-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Macronix MX25L51235F SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for MX25L25635FJagannadha Sutradharudu Teki2013-10-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Macronix MX25L25635F SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: ops: Add static qualifier to spi_flash_cmd_bankaddr_writeJagannadha Sutradharudu Teki2013-10-07-6/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Print erase_size while printing flash detailsJagannadha Sutradharudu Teki2013-10-07-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Included erase_size while printing probed flash details. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Use print_size arg as page_sizeJagannadha Sutradharudu Teki2013-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use flash->page_size arg in print_size() instead of flash->sector_size while printing detected flas part details. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for S25FL512S_256KJagannadha Sutradharudu Teki2013-10-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Spansion S25FL512S_256K SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for S25FL256S_256KJagannadha Sutradharudu Teki2013-10-07-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Spansion S25FL256S_256K SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for EN25Q64Jagannadha Sutradharudu Teki2013-10-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for EON EN25Q64 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: Remove unneeded flash drivers filesJagannadha Sutradharudu Teki2013-10-07-1508/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now the common probing is handled in spi_flash_probe.c hence removed the unneeded flash drivers. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: ramtron: Add support for separate flash driverJagannadha Sutradharudu Teki2013-10-07-284/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compared to other spi flashes, ramtron has a different probing and implementation on flash ops, hence moved ramtron probe code into ramtron driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: Add proper comment style on spi_flash structureJagannadha Sutradharudu Teki2013-10-07-28/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added proper comment style on spi_flash structure to make more readable. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Simply the BAR configuration logicJagannadha Sutradharudu Teki2013-10-07-54/+20
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for flag status pollingJagannadha Sutradharudu Teki2013-10-07-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Micron, 512MB onwards, flash requires to poll flag status instead of read status- hence added E_FSR flag on spectific flash parts. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for erase sector selection flagJagannadha Sutradharudu Teki2013-10-07-84/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SECT_4K, SECT_32K and SECT_64K opeartions are performed to to specific flash by adding a SECT* flag on respective spi_flash_params.flag param. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support to clear flash BP# bitsJagannadha Sutradharudu Teki2013-10-07-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Few of the flashes(Atmel, Macronix and SST) require to clear BP# bits in flash power ups. So clear these BP# bits at probe time, so-that the flash is ready for user operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for SST_WPJagannadha Sutradharudu Teki2013-10-07-77/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the SST flashes needs to write up using SST_WP, AAI Word Program, so added a flag param on spi_flash_params table. SST flashes, which supports SST_WP need to use a WP write sst_write_wp instead of common flash write. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Give proper spacing on flash table paramsJagannadha Sutradharudu Teki2013-10-07-77/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Given proper spacing between flash table params. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for AT45DB* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added AT45DB* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for SST25* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added SST25* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * | | | sf: probe: Add support for S25FL* flash partsJagannadha Sutradharudu Teki2013-10-07-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added S25FL* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for W25* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added W25* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for MX25L* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added MX25L* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for GD25* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added GD25* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for EN25Q* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added EN25Q* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add support for M25P* flash partsJagannadha Sutradharudu Teki2013-10-07-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added M25P* parts are which are avilable in spi_flash_probe_legacy.c. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: probe: Add new spi_flash_probe supportJagannadha Sutradharudu Teki2013-10-07-122/+385
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added new spi_flash_probe support, currently added N25Q* flash part attributes support. Updated the sector_size attributes as per the flash parts. Looks fine for with this sector_size for computing the size of flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | | sf: Divide spi_flash into multiple partsJagannadha Sutradharudu Teki2013-10-07-567/+596
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Divided the spi_flash framework into mutiple parts for - spi_flash.c: spi flash core file, interaction for spi/qspi driver to spi_flash framework. - spi_flash_ops.c spi flash preffered operations, erase,write and read. - spi_flash_probe.c spi flash probing, easy to extend probing functionality. This change will support to extend the functionality in a proper manner. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | | | Fix number base handling of "load" commandWolfgang Denk2013-10-07-23/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As documented, almost all U-Boot commands expect numbers to be entered in hexadecimal input format. (Exception: for historical reasons, the "sleep" command takes its argument in decimal input format.) This rule was broken for the "load" command; for details please see especially commits 045fa1e "fs: add filesystem switch libary, implement ls and fsload commands" and 3f83c87 "fs: fix number base behaviour change in fatload/ext*load". In the result, the load command would always require an explicit "0x" prefix for regular (i. e. base 16 formatted) input. Change this to use the standard notation of base 16 input format. While strictly speaking this is a change of the user interface, we hope that it will not cause trouble. Stephen Warren comments (see [1]): I suppose you can change the behaviour if you want; anyone writing "0x..." for their values presumably won't be affected, and if people really do assume all values in U-Boot are in hex, presumably nobody currently relies upon using non-prefixed values with the generic load command, since it doesn't work like that right now. [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/171172 Acked-by: Tom Rini <trini@ti.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | | pci: Properly configure prefetchable memory regionThierry Reding2013-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Forcibly set hose->pci_prefetch to NULL to make sure it will be setup. This will help if for any reason callers didn't make sure themselves to NULL the field. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | | | | ARM: virtualization: replace verbose license with SPDX identifierAndre Przywara2013-10-07-35/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S} predates the SPDX conversion, so the original elaborate license statements sneaked in. Fix this by replacing them with the proper abbreviation. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* | | | | doc: Fix a typo in the description in doc/README.JFFS2_NANDOtavio Salvador2013-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | | | | include/linux/fb.h: Add a missing include for 'list.h'Otavio Salvador2013-10-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The modelist data uses the list definition but the 'list.h' header were not being included. The build failure is bellow: ,---- | In file included from yyyy.c:16:0: | .../u-boot/include/linux/fb.h:503:19: error: field 'modelist' has incomplete type | struct list_head modelist; /* mode list */ | ^ | make[1]: *** [yyyy.o] Error 1 | make[1]: Leaving directory `.../u-boot/board/xxx/yyyy' | make: *** [board/xxx/yyyy/libyyyy.o] Error 2 `---- Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | | | | mtd: Fix function description in part_validate commentOtavio Salvador2013-10-07-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The part_validate comment had a wrong description of the actions it does and referenced to non-existent functions while in fact it calls 'part_validate_eraseblock()'. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | | | | power:pmic: prevent data abort for pmic bat commandPiotr Wilczek2013-10-07-8/+11
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch prevents data abort when pmic bat command is called on non-batery pmic device. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Lukasz Majewski <l.majewski@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-04-2/+476
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| * | | ARM: VExpress: enable ARMv7 virt support for VExpress A15Andre Przywara2013-10-03-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable hypervisors utilizing the ARMv7 virtualization extension on the Versatile Express board with the A15 core tile, we add the required configuration variable. Also we define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the VExpress specific manner. There is no need to provide a custom smp_waitloop() function here. This also serves as an example for what to do when adding support for new boards. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * | | ARM: extend non-secure switch to also go into HYP modeAndre Przywara2013-10-03-9/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the KVM and XEN hypervisors to be usable, we need to enter the kernel in HYP mode. Now that we already are in non-secure state, HYP mode switching is within short reach. While doing the non-secure switch, we have to enable the HVC instruction and setup the HYP mode HVBAR (while still secure). The actual switch is done by dropping back from a HYP mode handler without actually leaving HYP mode, so we introduce a new handler routine in our new secure exception vector table. In the assembly switching routine we save and restore the banked LR and SP registers around the hypercall to do the actual HYP mode switch. The C routine first checks whether we are in HYP mode already and also whether the virtualization extensions are available. It also checks whether the HYP mode switch was finally successful. The bootm command part only calls the new function after the non-secure switch. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * | | ARM: add SMP support for non-secure switchAndre Przywara2013-10-03-1/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. While this approach is pretty universal across several ARMv7 boards, we make this function weak in case someone needs to tweak this for a specific board. The way of setting the secondary's start address is board specific, but mostly different only in the actual SMP pen address, so we also provide a weak default implementation and just depend on the proper address to be set in the config file. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * | | ARM: trigger non-secure state switch during bootm executionAndre Przywara2013-10-03-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To actually trigger the non-secure switch we just implemented, call the switching routine from within the bootm command implementation. This way we automatically enable this feature without further user intervention. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * | | ARM: add C function to switch to non-secure stateAndre Przywara2013-10-03-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core specific part of the work is done in the assembly routine in nonsec_virt.S, introduced with the previous patch, but for the full glory we need to setup the GIC distributor interface once for the whole system, which is done in C here. The routine is placed in arch/arm/cpu/armv7 to allow easy access from other ARMv7 boards. We check the availability of the security extensions first. Since we need a safe way to access the GIC, we use the PERIPHBASE registers on Cortex-A15 and A7 CPUs and do some sanity checks. Boards not implementing the CBAR can override this value via a configuration file variable. Then we actually do the GIC enablement: a) enable the GIC distributor, both for non-secure and secure state (GICD_CTLR[1:0] = 11b) b) allow all interrupts to be handled from non-secure state (GICD_IGROUPRn = 0xFFFFFFFF) The core specific GIC setup is then done in the assembly routine. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
generated by cgit v1.1 at 2024-11-01 02:31:42 +0000