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* Move display_options functions to their own headerSimon Glass2015-04-29-28/+49
| | | | | | | | Before adding one more function, create a separate header to help reduce the size of common.h. Add the missing function comments and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Disable -WerrorSimon Glass2015-04-29-1/+1
| | | | | | | | | This is annoying during development and serves no useful purpose since warnings are clearly displayed now that we are using Kbuild. Remove this option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove unwanted MMC debuggingSimon Glass2015-04-29-1/+0
| | | | | | | This printf() should not have made it into the code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: core: Add a function to bind a driver for a device tree nodeSimon Glass2015-04-29-1/+24
| | | | | | | | Some device tree nodes do not have compatible strings but do require drivers. This is pretty rare, and somewhat unfortunate. Add a function to permit creation of a driver for any device tree node. Signed-off-by: Simon Glass <sjg@chromium.org>
* Fix comment nits in board_f.cSimon Glass2015-04-29-5/+4
| | | | | | | Try to make it a little clearer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Use reset_cpu()Simon Glass2015-04-29-7/+0
| | | | | | | | Now that reset_cpu() functions correctly, use it instead of directly accessing the port on boards that use a Firmware Support Package (FSP). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: quark: Use reset_cpu()Simon Glass2015-04-29-1/+1
| | | | | | | | | Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Use reset_cpu()Simon Glass2015-04-29-15/+6
| | | | | | | | Now that reset_cpu() functions correctly, use it instead of directly accessing the port. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Implement reset_cpu() correctly for modern CPUsSimon Glass2015-04-29-13/+28
| | | | | | | | | | | | The existing code is pretty ancient and is unreliable on modern hardware. Generally it will hang. We can use port 0xcf9 to initiate reset on more modern hardware (say in the last 10 years). Update the reset_cpu() function to do this, and add a new 'full reset' function to perform a full power cycle. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: link: Add PCH driver to support SPI FlashSimon Glass2015-04-29-1/+12
| | | | | | | | U-Boot on coreboot does not have a driver for the PCH so cannot see the SPI peripheral now that it has moved inside the PCH. Add a simple driver so that SPI flash works again. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Update chromebook_link instructions for binary blobSimon Glass2015-04-29-1/+1
| | | | | | | The MRC image is incorrect, or at least this one now does not seem to work. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: use the correct NOR in the configurationGabriel Huau2015-04-29-2/+2
| | | | | | | | The SPI NOR on the minnowboard max is a MICRON N25Q064A Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Correct the typo in write_tables()Bin Meng2015-04-29-1/+1
| | | | | | | It should be #ifdef instead of #if. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Kconfig: Remove deprecated CONFIG_SYS_EXTRA_OPTIONSBin Meng2015-04-29-7/+19
| | | | | | | | | Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define the text base address. Since it is deprecated, just remove it and use CONFIG_SYS_TEXT_BASE directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Kconfig: Move DM_SPI & DM_SPI_FLASH to arch/KconfigBin Meng2015-04-29-6/+2
| | | | | | | | Since all x86 boards have been converted to use DM_SPI and DM_SPI_FLASH, move them to arch/Kconfig x86 section. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Kconfig: MARK_GRAPHICS_MEM_WRCOMB cosmeticsBin Meng2015-04-29-4/+4
| | | | | | | | Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also fix the indention of its help text. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Kconfig: Move platform options forwardBin Meng2015-04-29-10/+9
| | | | | | | | | | | Move platform-specific options under in arch/x86/Kconfig forward right after the board-specific options but before any architecture-specific options. When it comes to the same Kconfig option, board-specific one takes take the highest precedence, then platform-specific one, and finally architecture-specific one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Kconfig: Divide the target selection to vendor/modelBin Meng2015-04-29-79/+139
| | | | | | | | | | Let arch/x86/Kconfig prompt board vendor first, then select the board model under that vendor. This way arch/x86/Kconfig only needs concern board vendor and leave the supported target list to board/<vendor>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Turn on legacy segments decodeBin Meng2015-04-29-0/+19
| | | | | | | | | By default the legacy segments (A0000h-B0000h, E0000h-F0000h) do not decode to system RAM. Turn on the decode so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Check PIRQ routing table sanity in the F segmentBin Meng2015-04-29-5/+13
| | | | | | | | | | Previously the PIRQ routing table sanity check was performed against the original table provided by the platform codes. Now we switch to check its sanity on the final table in the F segment as this one is the one seen by the OS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: add GPIO banks in the device treeGabriel Huau2015-04-29-0/+42
| | | | | | | | | | There are 6 banks: 4 banks for CORE: available in S0 mode 2 banks for SUS (Suspend): available in S0-S5 mode Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: fix the GPIOBASE addressGabriel Huau2015-04-29-1/+1
| | | | | | | | The correct GPIOBASE address on the baytrail is 0x48 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Correct Minnowboard instructions to use the right descriptorSimon Glass2015-04-29-3/+20
| | | | | | | The descriptor provided with the FSP does not seem to work. Update the instructions to use the descriptor from the original Intel firmware. Signed-off-by: Simon Glass <sjg@chromium.org>
* biosemu: Do not free vga_info->BIOSImage when it is 0xc0000Bin Meng2015-04-29-1/+2
| | | | | | | For x86, vga_info->BIOSImage points to 0xc0000 which cannot be freed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* pci: Remove parameter 'class' of pci_rom_load()Bin Meng2015-04-29-2/+2
| | | | | | | pci_rom_load() does not use its parameter 'class', so remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* pci: Option rom class is a 24-bit numberBin Meng2015-04-29-9/+11
| | | | | | | We should pass a u32 class number to pci_rom_probe() instead of a u16. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Implement PIRQ routingBin Meng2015-04-29-4/+442
| | | | | | | | Implement Intel Queensbay platform-specific PIRQ routing support. The chipset PIRQ routing setup is called in the arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Support platform PIRQ routingBin Meng2015-04-29-0/+300
| | | | | | | | | | | | | | | On x86 boards, platform chipset receives up to four different interrupt signals from PCI devices (INTA/B/C/D), which in turn will be routed to chipset internal PIRQ lines then routed to 8259 PIC finally if configuring the whole system to work under the so-called PIC mode (in contrast to symmetric IO mode which uses IOAPIC). We add two major APIs to aid this, one for routing PIRQ and the other one for generating a PIRQ routing table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Write configuration tables in last_stage_init()Bin Meng2015-04-29-0/+91
| | | | | | | | We can write the configuration table in last_stage_init() for all x86 boards, but not with coreboot since coreboot already has them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add a function to assign IRQ numbers to PCI deviceBin Meng2015-04-29-0/+35
| | | | | | | | | Add a function to assign an IRQ number to PCI device's interrupt line register in its configuration space, so that the PCI device can have its interrupt working under PIC mode after OS boots up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Install a default e820 table in the __weak install_e820_map()Bin Meng2015-04-29-7/+22
| | | | | | | | Create a default e820 table with 3 entries which is enough to boot a Linux kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Clean up arch/x86/include/asm/e820.hBin Meng2015-04-29-131/+2
| | | | | | | There are lots of unused codes defined in e820.h, clean it up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add alias for SPI node in the board dtsBin Meng2015-04-29-2/+11
| | | | | | | | | Since Intel ICH SPI driver has been converted to driver model, we need add an alias for SPI node in the board dts files otherwise SPI flash won't be detected due to 'invalid bus' error. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Set serial port IRQ for SMSC LPC47MBin Meng2015-04-29-4/+9
| | | | | | | | | For starting a Linux console on the superio serial port under interrupt mode, the IRQ number must be configured. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move CONFIG_ENV_IS_IN_SPI_FLASH to x86-common.hBin Meng2015-04-29-9/+8
| | | | | | | | | | Since all x86 boards use spi flash as its bootloader storage media, it makes sense to make CONFIG_ENV_IS_IN_SPI_FLASH a common option. So far only minnowmax board does not support it so undefine it in its board configuration file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Avoid using PCH prefixBin Meng2015-04-29-4/+3
| | | | | | | | | | The prefix PCH was taken from ivybridge port. However Queensbay platform official document does not mention PCH. It is composed of TunnelCreek processor and Topcliff IOH chipset. For accuracy, avoid using PCH prefix in the macro. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Remove the old VGA driverBin Meng2015-04-29-212/+0
| | | | | | | CONFIG_VIDEO_VGA is no longer needed thus remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: minnowmax: Remove CONFIG_VIDEO_X86 in the defconfigBin Meng2015-04-29-1/+0
| | | | | | | CONFIG_VIDEO_X86 has been replaced by CONFIG_VIDEO_VESA. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-04-29-50/+914
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| * ARM: zynq: rename CONFIG_ZYNQ to CONFIG_ARCH_ZYNQMasahiro Yamada2015-04-29-12/+12
| | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: move SoC headers to mach-zynq/include/machMasahiro Yamada2015-04-29-0/+0
| | | | | | | | | | | | | | | | Move arch/arm/include/asm/arch-zynq/* -> arch/arm/mach-zynq/include/mach/* Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: move SoC sources to mach-zynqMasahiro Yamada2015-04-29-4/+4
| | | | | | | | | | | | | | Move arch/arm/cpu/armv7/zynq/* -> arch/arm/mach-zynq/* Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: pass "-mfpu=neon" only to lowlevel_init.SMasahiro Yamada2015-04-29-7/+1
| | | | | | | | | | | | | | | | | | The comment line in arch/arm/cpu/armv7/zynq/config.mk says that the option "-mfpu=neon" is necessary for compiling lowlevel_init.S. We do not have to give it to all the source files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: Enable SDHCI0 optionsMichal Simek2015-04-29-0/+14
| | | | | | | | | | | | | | Enable SDHCI0 for zynqmp. Add empty gpio.h because of sdhci requirement. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: Enable FS_GENERIC optionSiva Durga Prasad Paladugu2015-04-29-2/+3
| | | | | | | | | | | | | | Provide an option to write filesystem independend commands. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: Add SPI driver support for ZynqMPSiva Durga Prasad Paladugu2015-04-29-0/+10
| | | | | | | | | | | | | | | | | | Added the SPI driver support for ZynqMP The controller is same as zynq SPI controller Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * zynqmp: i2c: Enable i2c driver for zynqMPSiva Durga Prasad Paladugu2015-04-29-0/+26
| | | | | | | | | | | | | | | | | | | | Enable the i2c driver for ZynqMP Also enable the eeprom for read and writes to eeprom on ZynqMP ZynqMP uses the same i2c controller as in Zynq Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: Add support for EMMC bootmodeMichal Simek2015-04-29-1/+3
| | | | | | | | | | | | Add support for EMMC bootmode. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynqmp: Add support for emulation platform - VeloceMichal Simek2015-04-29-2/+12
| | | | | | | | | | | | | | Add support for Veloce - zynqmp emulation platform. Platform doesn't support SDHCI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * zynq: timer: Fix wrong timer calculationSiva Durga Prasad Paladugu2015-04-29-1/+3
| | | | | | | | | | | | | | | | | | | | Fix wrong timer calculation in get_timer_masked incase of overflow. This fixes the issue of getting wrong time from get_timer() calls. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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