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| author | Gabriel Huau <contact@huau-gabriel.fr> | 2015-04-25 08:13:11 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-04-29 18:51:50 -0600 |
| commit | 8ddb8cfb1a4edee9c413381b5350e62b0ed701a0 (patch) | |
| tree | d1196b8752a31471e4b47da188d78983b823daa8 | |
| parent | cc4c8aca1de4a0a6ef81460217f64c4b76de5340 (diff) | |
| download | u-boot-imx-8ddb8cfb1a4edee9c413381b5350e62b0ed701a0.zip u-boot-imx-8ddb8cfb1a4edee9c413381b5350e62b0ed701a0.tar.gz u-boot-imx-8ddb8cfb1a4edee9c413381b5350e62b0ed701a0.tar.bz2 | |
x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | arch/x86/dts/minnowmax.dts | 2 | ||||
| -rw-r--r-- | include/configs/minnowmax.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 4be227a..0233f61 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -74,7 +74,7 @@ compatible = "intel,ich-spi"; spi-flash@0 { reg = <0>; - compatible = "sst,25vf016b", "spi-flash"; + compatible = "stmicro,n25q064a", "spi-flash"; memory-map = <0xff800000 0x00800000>; }; }; diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 6dbae8f..2a1915d 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -42,7 +42,7 @@ #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA} -#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_MMC #define CONFIG_SDHCI |