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* sunxi: musb: Remove unused sunxi_musb_exit methodHans de Goede2015-06-17-34/+0
| | | | | | | | | Remove the unused sunxi_musb_exit method, there is no code in u-boot calling the exit method, and our implementation was broken as it did not disable the clocks and asserted reset. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: musb: Do not fully reset the controler from sunxi_musb_disableHans de Goede2015-06-17-21/+31
| | | | | | | | | | | | | | Fully resetting the controller is a too big hammer, and the musb_core will then afterwards fail to communicate with any endpoints other then 0 as too much state was cleared. Instead report vbus low for 200ms which will effectively end the current session without needing to do a full reset. This fixes usb mass-storage devices no longer working after a "usb reset" Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* Merge git://git.denx.de/u-boot-usbTom Rini2015-06-15-13/+364
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| * samsung: common: add example boot scriptsPrzemyslaw Marczak2015-06-08-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds example scripts of boot.scr: - bootzimg.cmd - check if dtb exists and boot zImage - autoboot.cmd - check which image exists: Image.itb, zImage or uImage and optionally load fdt file for u/zImage The blank spaces are added to improve readability and can be removed before use mkimage. Required U-Boot environment variables: $boardname, $fdtfile, $console, $mmcbootdev, $mmcbootpart, $mmcrootdev, $mmcrootpart, $rootfstype. Making boot.scr from file.cmd: mkimage -C none -A arm -T script -d file.cmd boot.scr The Odroid XU3 default environment is ready for those boot scripts and the right script can be loaded by DFU. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * odroid-xu3: config: enable DFU/THOR/UMS by add configs and environmentPrzemyslaw Marczak2015-06-08-2/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables all functions required to use DFU/THOR and UMS: - DWC3: core, gadget, Samsung DWC3 PHY - USB gadget: endpoint autoconf, downloader, DFU, THOR, UMS The CONFIG_EXTRA_ENV_SETINGS from exynos5-common.h is redefined and appended by dfu environment setting and some system settings. The boot is still using $distro_boot as previous. Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * usb: f_mass_storage: sleep_thread: decrease the interval for check ctrlc()Inha Song2015-06-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This change decreases the interval of calls to: - display busy indicator - check ctrlc() - check cable connection By this change, breaking the UMS command is more easy on Odroid XU3. Signed-off-by: Inha Song <ideal.song@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * smdk5420: board: add functions to init dfu environment settingsInha Song2015-06-08-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit extends SMDK5420 board's file by adding functions: - get_dfu_alt_system() - get_dfu_alt_boot() This allows setting the DFU environment by function set_dfu_alt_info() from: board/samsung/common/misc.c Signed-off-by: Inha Song <ideal.song@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * smdk5420: board: add functions required to enable USB DWC3Joonyoung Shim2015-06-08-8/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds implementation of function calls: - usb_gadget_handle_interrupts() - board_usb_init() Which allow enable USB DWC3 gadget for this board. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Inha Song <ideal.song@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * samsung: usb: phy: Support for DWC3 PHYLukasz Majewski2015-06-08-0/+95
| | | | | | | | | | | | | | | | | | | | | | New files, namely samsung_usb_phy.c and samsung-usb-phy-uboot.h have been added to u-boot to provide proper PHY handling at Exynos5 SoCs. This code is used thereafter in the board_usb_init() call. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * arm: exynos: USB3 PHY base definition for Exynos5 SoCsLukasz Majewski2015-06-08-1/+1
| | | | | | | | | | | | | | | | After that change it would be possible to call samsung_get_base_usb3_phy() function to get proper base address Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * drivers: usb: fsl: Return if USB_MAX_CONTROLLER_COUNT is incorrectNikhil Badola2015-06-07-1/+1
| | | | | | | | | | | | | | Return if USB_MAX_CONTROLLER_COUNT hence the index of the controller to be initialised is incorrect Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2015-06-15-12/+39
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| * | tools/kwboot: Add parameters to set delay and timeout via cmdlineStefan Roese2015-06-14-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support the Armada 38x, new values for the request-delay and the response-timeout are needed. As the values already implemented in this tool (for Kirkwood and Armada XP) don't seem to work here. To make this more flexible, lets add make those 2 parameters configurable via the cmdline. Here the new parameters: -q <req-delay>: use specific request-delay -s <resp-timeo>: use specific response-timeout For the Marvell DB-88F6820 these values are known to work: One board: -q 2 -s 1 2nd board: -q 5 -s 5 So this seems to be even board specific. But with this patch now those values can be specified and tested via the cmdline. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Update CBAR with SOC regs baseKevin Smith2015-06-14-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | SMP-enabled Linux kernels read the CBAR register in CP15 to find the address of the SCU registers. After remapping internal registers, also update the CBAR so the kernel can find them. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: Disable L2 cache before enabling d-cacheStefan Roese2015-06-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | L2 cache may still be enabled by the BootROM. We need to first disable it before enabling d-cache support. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
| * | tools/kwbimage.c: Correct header size for SPI bootKevin Smith2015-06-14-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If defined, the macro CONFIG_SYS_SPI_U_BOOT_OFFS allows a board to specify the offset of the payload image into the kwb image file. This value was being used to locate the image, but was not used in the "header size" field of the main header. Move the use of this macro into the function that returns the header size so that the same value is used in all places. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Stefan Roese <sr@denx.de>
* | | omap5: Exclude more environment from SPL buildsTom Rini2015-06-15-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | In the cases where we make use of environment in SPL we do not need these defaults compiled in and available. These are taking up space that in some cases now prevent linking, so drop. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | board: add support for Vision System's Baltos Industrial PCYegor Yefremov2015-06-15-0/+1280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vision Systems's Baltos is based on AM335x SoC from Texas Instruments. This patch adds support such Industrial PCs in mainline u-boot. [ balbi@ti.com: updated original patch to current u-boot ] Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* | | ARM: DRA7: emif: Fix DDR init sequence during warm resetLokesh Vutla2015-06-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after warm reset, emif needs to be configured to bring it back to a known state. So configure EMIF during warm reset. Reported-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | avr32: move CONFIG_SYS_GENERIC_BOARD to KconfigMasahiro Yamada2015-06-15-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | Now all the AVR32 boards have been converted into Generic Board. Select it in Kconfig and clean up defines in header files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | ARM: AM43x: Fix MAX_RAM_BANK_SIZELokesh Vutla2015-06-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On AM437x-GP Evm there is 2GB of DDR3 memory available as stated in AM437x GP EVM HardwareUser's guide http://www.ti.com/lit/ug/spruhw7/spruhw7.pdf. But MAX_RAM_BANK_SIZE is defined as 1GB. Fixing MAX_RAM_BANK_SIZE to 2GB on AM43xx. Reported-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | am33xx: Re-enable SW levelling for DDR2Tom Rini2015-06-15-40/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recent changes for hw leveling on am33xx were not intended for DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config value to check against. This lets us pass in the value we would use to configure, when we have not yet configured the board yet. In other cases update the call to be as functional as before and check an already programmed value in. Tested-by: Yan Liu <yan-liu@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: BeagleBoard-x15: Enable i2c5 clocksLokesh Vutla2015-06-15-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | On AM57xx evm I2C5 is used to detect the LCD board by reading the EEPROM present on the bus. Enable i2c5 clocks to help that. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | am43xx_evm: Enable NAND bootTom Rini2015-06-15-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | Enable booting from NAND on the am437xx-evm. Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | am335x_evm: nand: Fix boot from NANDRoger Quadros2015-06-15-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use the correct partition names from with the Device Tree blob and the kernel is picked up. Also use partition name instead of number for the root filesystem in the kernel boot arguments. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | am335x_evm: am44xx_evm: dra7xx_evm: nand: Fix file-system partition nameRoger Quadros2015-06-15-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We almost always use UBIFS for user accessible NAND file systems and the UBIFS file system might contain more than one volume within the single NAND partition. The last NAND partition is therefore more appropriately named as "NAND.file-system" instead of "NAND.rootfs" The Linux kernel (as of v3.16) also uses "NAND.file-system" to name the last NAND partition. This patch makes the partition name consistent between u-boot and the kernel. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | configs: am43xx_evm: Enable NANDRoger Quadros2015-06-15-1/+1
| | | | | | | | | | | | | | | | | | | | | AM43xx EVMs have NAND so enable it. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | highbank: add custom ahci_link_up functionMark Langsdorf2015-06-15-1/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Calxeda highbank SOC needs a custom sequence to bring up SATA links, so override ahci_link_up with custom function to handle combophy setup. Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Richard Gibbs Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Andre Przywara <osp@andrep.de>
* | | ahci: extend data io wait to 10sMark Langsdorf2015-06-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AHCI driver currently waits 5s before timing out when sending a data command to a drive. Some drives take upwards of 8s to respond to the initial data command while they're spinning up. Increase the data io timeout to 10s so that those drives can be found on initial scsi scan. Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de>
* | | ahci: support LBA48 data reads for 2+TB drivesMark Langsdorf2015-06-12-11/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable full 48-bit LBA48 data reads by passing the upper word of the LBA block pointer in bytes 9 and 10 of the FIS. This allows uboot to load data from any arbitrary sector on a drive with 2 or more TB of available data connected to an AHCI controller. Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de> [trini: Make use of CONFIG_SYS_64BIT_LBA in a few places to drop warnings on platforms that don't enable that feature ] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | cmd_scsi: use lbaint_t for LBA values instead of u32Mark Langsdorf2015-06-12-7/+7
| | | | | | | | | | | | | | | Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de>
* | | ARM: highbank: add reset support for Calxeda Midway machineMark Langsdorf2015-06-12-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Calxeda Midway part has A15 cores, which do not have the Highbank A9's SCU used there for resetting the chip. Add code to distinguish between the A9 and the A15 and invoke the appropriate register writes to support the newer part. Andre: rework detection of Highbank vs. Midway Rob: fix Andre's reworked detection Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de> Signed-off-by: Rob Herring <robh@kernel.org>
* | | ARM: highbank: add missing SCU register setup for resetRob Herring2015-06-12-0/+6
| | | | | | | | | | | | | | | | | | | | | Andre: assign names to the magic values Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Andre Przywara <osp@andrep.de>
* | | ARM: BeagleBoard-x15: Add mux dataLokesh Vutla2015-06-12-38/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the mux data, manual and virtual mode settings for BeagleBoard-X15. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
* | | ARM: BeagleBoard-x15: Enable IO delay recalibration sequenceLokesh Vutla2015-06-12-3/+15
| | | | | | | | | | | | | | | | | | | | | Enable IO delay recalibration sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: CPSW: Remove IO delay hackLokesh Vutla2015-06-12-91/+0
| | | | | | | | | | | | | | | | | | | | | | | | Now all manual mode configurations are done as part of IO delay recalibration sequence, remove the hack done for CPSW. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7-evm: Add mux dataNishanth Menon2015-06-12-27/+326
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the mux data, manual and virtual mode settings for DRA7-evm. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
* | | ARM: DRA7-evm: Enable IO delay recalibration sequenceLokesh Vutla2015-06-12-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling IO delay recalibration sequence for DRA7 EVM. UART and I2C are configured before IO delay recalibration sequence as these are used earlier and safe to use. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Add support for manual mode configurationLokesh Vutla2015-06-12-2/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "manual mode" also programmed, when predefined delay characteristics cannot be used for the interface. struct iodelay_cfg_entry is introduced for populating manual mode IO timings. For configuring manual mode, along with the normal pad configuration do the following steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux) - Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL. And pass the offset of the CFG_XXX register in iodelay_cfg_entry. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Add support for IO delay configurationLokesh Vutla2015-06-12-0/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA7, in addition to the regular muxing of pins, an additional hardware module called IODelay which is also expected to be configured. This "IODelay" module has it's own register space that is independent of the control module. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay recalibration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do muxing as part of IOdelay recalibration. IODELAY recalibration sequence: - Complete AVS voltage change on VDD_CORE_L - Unlock IODLAY config registers. - Perform IO delay calibration with predefined values. - Isolate all the IOs - Update the delay mechanism for each IO with new calibrated values. - Configure PAD configuration registers - De-isolate all the IOs. - Relock IODELAY config registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Add support for virtual mode configurationLokesh Vutla2015-06-12-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "virtual mode" also programmed. This allows for predefined delay characteristics to be used by the SoC to meet timing characterstics needed for the interface. Provide easy to use macro to do the same. For configuring virtual mode, along with normal pad configuration add the following two steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1 - DELAYMODE filed should be configured with value given in DATA Manual. CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Add pinctrl register definitionsLokesh Vutla2015-06-12-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adopting the pinctrl register definitions from Linux kernel to be consistent. Old definitions will be removed once all the pinctrl data is adapted to new definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7: Make do_set_mux32() genericLokesh Vutla2015-06-12-20/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | do_set_mux32() is redefined in dra7xx and beagle_x15 boards. IO delay recalibration sequence also needs this. Making it generic to avoid duplication. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* | | ARM: DRA7xx: EMIF: Fix DLL_CALIB_CTRL registerLokesh Vutla2015-06-12-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | When DLL_CALIB_INTERVAL is set, an extra delay is added which is not required and it consumes EMIF bandwidth. So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | ARM: DRA7: Update DDR IO registersLokesh Vutla2015-06-12-8/+8
| | | | | | | | | | | | | | | | | | | | | Update DDR IO register values. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: Update DDR IO configurationLokesh Vutla2015-06-12-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | DDRIO_2 and LPDDR2CH1_1 registers are not present for DRA7. So not configuring these registers for DRA7xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7: Add is_dra72x cpu check definitionLokesh Vutla2015-06-12-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | A generic is_dra72x cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA72-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on DRA72-evm. Also updating the timing registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7-evm: Enable HW levelingLokesh Vutla2015-06-12-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on DRA7-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: BeagleBoard-X15: Enable HW levelingLokesh Vutla2015-06-12-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | Updating EMIF registers to enable HW leveling on BeagleBoard-X15. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-12-28 00:56:32 +0000