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* arm: socfpga: clock: Sync with reference codeMarek Vasut2014-10-06-16/+29
| | | | | | | | | | | | | | | Add the missing pieces from the reference clock code from Altera. This puts the code on par with the Altera U-Boot fork for all but the SDRAM self-refresh bits, which are not part of this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: clock: Clean up bit definitionsMarek Vasut2014-10-06-303/+323
| | | | | | | | | | | | | | Clean up the clock code definitions so they are aligned with mainline standards. There are no functional changes in this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: clock: Trim down code duplicationMarek Vasut2014-10-06-58/+38
| | | | | | | | | | | | | | | Pull out functions to read frequency of Main clock VCO and PLL clock VCO as the code is duplicated multiple times. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: clock: Add code to read clock configurationPavel Machek2014-10-06-3/+267
| | | | | | | | | | | | | | | | | | Add the entire bulk of code to read out clock configuration from the SoCFPGA CPU registers. This is important for MMC, QSPI and UART drivers as otherwise they cannot determine the frequency of their upstream clock. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Fixed the L4 MP clock divider and synced the clock code with latest rocketboards codebase (thanks Dinh for pointing this out)
* arm: socfpga: clock: Add missing stubs into board fileMarek Vasut2014-10-06-0/+3
| | | | | | | | | | | | | | | Add some stub defines, which are used by the clock code, but are missing from the auto-generated header file for the SoCFPGA family. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: clock: Drop nonsense inlining from clock manager codeMarek Vasut2014-10-06-6/+6
| | | | | | | | | | | | | | | | The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Scrub this hint. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: clock: Implant order into bit definitionsMarek Vasut2014-10-06-67/+99
| | | | | | | | | | | | | | The bit definitions for clock manager are complete chaos. Implement some basic logical order into them. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: sysmgr: Clean up system managerMarek Vasut2014-10-06-34/+86
| | | | | | | | | | | | | | Clean up the system manager register definition and add the missing register definitions in place. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add watchdog disable for socfpgaPavel Machek2014-10-06-0/+30
| | | | | | | | | | | | | | | | This adds watchdog disable. It is neccessary for running Linux kernel. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
* arm: socfpga: Clean up base address fileMarek Vasut2014-10-06-51/+51
| | | | | | | | | | | | | | | Sort the list of functional block addresses and fix indentation. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
* arm: socfpga: Complete the list of base addressesPavel Machek2014-10-06-0/+40
| | | | | | | | | | | | | | | Add base addresses for all subsystems as documented in the Cyclone V HPS documentation. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
*-----. Merge branches 'topic/drivers/fpga-20141006', 'topic/drivers/mmc-20141006', ↵Marek Vasut2014-10-06-42/+317
|\ \ \ \ | | | | | | | | | | | | | | | 'topic/drivers/net-20141006', 'topic/tools/mkimage-20141006' and 'topic/arm/cache-20141006' into HEAD
| | | | * arm: cache: Add support for write-allocate D-CacheMarek Vasut2014-10-06-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| | | * | tools: socfpga: Add socfpga preloader signing to mkimageCharles Manning2014-10-06-0/+265
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like many platforms, the Altera socfpga platform requires that the preloader be "signed" in a certain way or the built-in boot ROM will not boot the code. This change automatically creates an appropriately signed preloader from an SPL image. The signed image includes a CRC which must, of course, be generated with a CRC generator that the SoCFPGA boot ROM agrees with otherwise the boot ROM will reject the image. Unfortunately the CRC used in this boot ROM is not the same as the Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a CRC but is more correctly described as a checksum. Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c. Signed-off-by: Charles Manning <cdhmanning@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de> V2: - Zap unused constant - Explicitly print an error message in case of error - Rework the hdr_checksum() function to take the *header directly instead of a plan buffer pointer
| | * | net: dwc: Make the cache handling less crypticMarek Vasut2014-10-06-25/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a few new variables to make the cache handling less cryptic. Add a variable for DMA and DATA descriptor start and end, so the correctness of the code is easier to inspect. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
| | * | net: dwc: Fix cache alignment issuesMarek Vasut2014-10-06-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix remaining cache alignment issues in the DWC Ethernet driver. Please note that the cache handling in the driver is making the code hideous and thus the next patch cleans that up. In order to make this change reviewable though, the cleanup is split from it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Pavel Machek <pavel@denx.de>
| | * | net: phy: Cleanup drivers/net/phy/micrel.cPavel Machek2014-10-06-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Old saying says that more than three exclamation marks in a row are sign of mental disease. Cleanup micrel.c. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Chin Liang See <clsee@altera.com>
| | * | net: Remove unused CONFIG_DW_SEARCH_PHY from configsPavel Machek2014-10-06-2/+0
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove this symbol from configs, since it's unused. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Chin Liang See <clsee@altera.com>
| * | mmc: dw_mmc: Fix cache alignment issueMarek Vasut2014-10-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA descriptors used by the DW MMC block must be aligned to cacheline size, otherwise we are unable to properly flush/inval cache over them and we get data corruption. The reason I chose this approach of expanding the structure is because the driver allocates the descriptors in bulk. This approach does waste space by inserting slop inbetween the descriptors, but it makes access to the descriptors easy as the compiler does know the real size of the structure. It also makes cache operations easy, since the size of the structure is cache aligned and the structure start address is as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Pavel Machek <pavel@denx.de>
| * | mmc: dw_mmc: cleanupsPavel Machek2014-10-06-12/+22
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dw_mmc driver was responding to errors with debug(). Change that to prinf()/puts() respectively so that any errors are immediately obvious. Also adjust english in comments. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Chin Liang See <clsee@altera.com>
* | fpga: altera: Turn the switches into table lookupMarek Vasut2014-10-06-111/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a table of FPGA family with matching functions associated with it and make all the code just look up the family in that table and call the associated function instead of the horrible switch voodoo which was duplicated all over the place. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* | fpga: altera: Clean up enums in altera.hMarek Vasut2014-10-06-27/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of the line-over-80 problems and zap the typedef that went alongside those enums. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* | fpga: altera: Make altera_validate return normal valuesMarek Vasut2014-10-06-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the function return either 0 or -EINVAL, that is, normal expected error codes and success codes instead of true/false nonsense. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* | fpga: altera: Move altera_validate to the topMarek Vasut2014-10-06-32/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the function to the top of the file to avoid forward declaration. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* | fpga: altera: More indentation trimdownMarek Vasut2014-10-06-118/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Further improve the indentation in the rest of the file, where the indentation is initially a bit less brutal. There is no functional change in this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* | fpga: altera: Clean up altera_validate functionMarek Vasut2014-10-06-22/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Boldly go, where no programmer has gone before and just clean up the indentation mayhem. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
* | fpga: altera: Clean up the printing and debugMarek Vasut2014-10-06-59/+58
|/ | | | | | | | | | | | | | Clean up the printf() statements and get rid of the PRINTF() macro by replacing it with debug_cond(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* Merge branch 'for-tom' of git://git.denx.de/u-boot-dmTom Rini2014-09-26-110/+89
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| * spi: Add brackets and tidy defines in spi.hSimon Glass2014-09-26-12/+12
| | | | | | | | | | | | | | | | Some of the #defines in spi.h are not bracketed. To avoid future mistakes add brackets. Also add an explanatory comment for SPI_CONN_DUAL_... Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * dm: spi: Move cmd device code into its own functionSimon Glass2014-09-26-21/+32
| | | | | | | | | | | | | | | | In preparation for changing the error handling in this code for driver model, move it into its own function. Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: config: Enable all SPI flash chipsSimon Glass2014-09-26-1/+7
| | | | | | | | | | | | | | | | | | Sandbox may as well support everything. This increases the amount of code that is built/tested by sandbox, and also provides access to all the supported SPI flash devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sandbox: Convert SPI flash emulation to use sf_paramsSimon Glass2014-09-26-76/+38
| | | | | | | | | | | | | | | | | | | | | | At present sandbox has its own table of supported SPI flash chips. Now that the SPI flash system is fully consolidated and has its own list, sandbox should use that. This enables us to expand the number of chips that sandbox supports. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-09-26-251/+1018
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| * | board/ls1021aqds: Add DDR4 supportYork Sun2014-09-25-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig for this variant to enable DDR4 support. RAW timing parameters are not added for DDR4. The board timing parameters are only tuned for single- rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM availability. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com>
| * | driver/ddr/fsl: Fix DDR4 driverYork Sun2014-09-25-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/ls2085a: Move u-boot location to make room for RCWYork Sun2014-09-25-1/+1
| | | | | | | | | | | | | | | | | | When booting with SP, RCW resides at the beginning of IFC NOR flash. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/ls2085a: Enable secondary coresYork Sun2014-09-25-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spin table is at the very beginning of boot code. Each core has an individual release address within the spin table, the ft_cpu_setup fn updates the "cpu-release-addr" property of each cpu node with the corresponding release address. Also fix CPU_RELEASE_ADDR to point to secondary_boot_func. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
| * | armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot PageYork Sun2014-09-25-89/+518
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
| * | fdt_support: Make of_bus_default_count_cells non staticArnab Basu2014-09-25-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_bus_default_count_cells can be used to get the #address-cells and #size-cells defined by the current node's parent node. This is required when using of_read_number to read from FDT nodes that can be 32 or 64 bytes depending on values defined by the parent. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> CC: Scott Wood <scottwood@freescale.com>
| * | fdt_support: Move of_read_number to fdt_support.hArnab Basu2014-09-25-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is being done so that it can be used outside 'fdt_support.c'. Making life more convenient when reading device node properties that can be 32 or 64 bits long. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Cc: Scott Wood <scottwood@freescale.com>
| * | driver/ddr/fsl: Fix tXP and tCKEYork Sun2014-09-25-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory blockYork Sun2014-09-25-5/+89
| | | | | | | | | | | | | | | | | | | | | DP-DDR is used for DPAA, separated from main memory pool for general use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit). Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr: Restruct driver to allow standalone memory spaceYork Sun2014-09-25-108/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
| * | board/ls2085a: Add support of NOR and NAND flash for simulatorPrabhakar Kushwaha2014-09-25-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of NOR and NAND flash for simulator target. Here IFC - CS0: NOR flash IFC - CS1: NAND flash Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/mtd: Use generic timer API for FSL IFC, eLBCPrabhakar Kushwaha2014-09-25-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's flash control driver is using architecture specific timer API i.e. usec2ticks Replace usec2ticks with get_timer() (generic timer API) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/ls2085a: Update env_addr after NOR flash relocationPrabhakar Kushwaha2014-09-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2085a has 2 regions in system memory map. Region1 is default map from where system boots. Once u-boot is moved to DDR, IFC is re-mapped to Region2. So, update gd->env_addr to reflect correct address. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-09-26-39/+82
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| * | powerpc: add --bss-plt to LDFLAGSChris Packham2014-09-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With some versions of gcc (that we know of 4.6.3 and 4.8.2 are affected) it is necessary to specify --bss-plt to get the final blrl in the _GOT2_TABLE_. Without this the last symbol does not get it's address relocated. For the P2041RDB board this ended up being NetArpWaitTimerStart which caused the ARP packets to timeout immediately. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/t1040qds: Add sgmii ports support in 0xA7 protocolPriyanka Jain2014-09-24-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042QDS (T1042 is T1040 Personality without L2 switch) supports following sgmii interfaces with serdes protocol 0xA7 -SGMII-MAC3 on Lane B - slot 7 -SGMII-MAC5 on Lane H - slot 7 -SGMII2.5G-MAC1 on Lane C - slot 6 -SGMII2.5G-MAC2 on Lane D - slot 5 Add support of above sgmii interfaces Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
| * | powerpc/t104xrdb: Set DDR ODT to 75ohmPriyanka Jain2014-09-24-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR-ODT require cfg_dram_type switch set properly as per DDR type. T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type should be set to OFF for DDR3L Update t104xrdb/README for switch setting Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-19 12:45:40 +0000