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* MLK-14693 mx7ulp: Change PLL rate calculation to avoid div 0rel_imx_4.1.33_7ulp_betaimx_v2016.03_4.1.33_7ulp_betaYe Li2017-04-14-2/+8
| | | | | | | | | | | | | The new ROM patch will set DENOM and NUM of APLL and SPLL to 0 to workaround PLL issue. When DENOM is 0, the PLL rate calculation will divide 0 and raise a signal. raise: Signal # 8 caught To avoid such problem, we change our calculation. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit f28cf489e1b3864bac6bae4944d8a73bab30ec32)
* MLK-14689 mx7ulp: Workaround APLL PFD2 to 345.6MhzYe Li2017-04-14-2/+2
| | | | | | | | | | The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28) to workaround the problem. The correct fix should let GPU handle the clock rate in kernel. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit e931d534fd68e0e639082766de17a20e705fd908)
* MLK-14533 mx7ulp_evk: Change APLL and its PFD0 frequenciesYe Li2017-03-28-2/+26
| | | | | | | | | | | | | | | | | | | | | | To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is 201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs are higher than this max rate. The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus. Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12), with settings: PFD0 FRAC: 32 APLL MULT: 22 APLL NUM: 2 APLL DENOM: 5 Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Fancy Fang <chen.fang@nxp.com> (cherry picked from commit 91be2789a93288cc087cd9e8db522c8308ef007c)
* MLK-14483 mx7ulp: Fix SPLL/APLL clock rate calculation issueYe Li2017-03-17-2/+6
| | | | | | | | The num/denom is a float value, but in the calculation it is convert to integer 0, and cause the result wrong. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 4a8f51499ca098637e9ee2036066374d34458865)
* MLK-14481 mx7ulp: Fix build issue when using M4 boot configurationYe Li2017-03-17-1/+1
| | | | | | | | Wrong SIZE_64K and SIZE_128K are used, and cause build break. Fix them in the patch. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit ef2a8a4d7e0c4557abf50dadb6f149afd5bfe956)
* MLK-14480 mx7ulp_evk: Add netboot to default boot commandYe Li2017-03-17-0/+1
| | | | | | | | Add netboot to CONFIG_BOOTCOMMAND, so when loadimage from SD fails, it can continue to boot from network. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit c1c23ff6ead15fa0dd080a091cfd7c5ad8469893)
* MLK-14417 imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platformsYe Li2017-03-14-7/+41
| | | | | | | | | | | | According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed". ROM sets this bit in normal boot flow, but when in serial download mode, it is not set. Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms, including mx7d, mx6ul/ull and mx7ulp. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 14990af03450f3e1898135c86fd8b93328007617)
* MLK-14312 mx7ulp: Fix incorrect DTB modification after using USBYe Li2017-03-02-16/+43
| | | | | | | | | | | | | | u-boot has feature that when booting for mfgtool, the u-boot will modify the DTB to disable SD 1.8v switch. But the judgement for mfgtool boot has a problem, it only checks whether the USB PHY power status is enabled. When a USB device (for example a USB ethernet) is used in u-boot, the power status is also enabled. So the u-boot incorrectly disable the SD 1.8v switch. The patch changes the get_boot_device to use the boot SW info provided by ROM. Only if it is a USB boot, we will start the DTB modification for SD. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 1fb61cd80af59c39d1ca01d833f566628ba48f32)
* MLK-13929-6 mx7ulp_evk: Enable the MIPI DSI splashscreenYe Li2017-02-16-2/+93
| | | | | | | Enable and setup board level codes for MIPI DSI splashscreen on EVK board. User needs set env variable"panel=HX8363_WVGA" for displaying. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13929-5 mx7ulp: Update clock and SoC functions for videoYe Li2017-02-16-0/+88
| | | | | | | | Add the clocks functions for enabling LCDIF and DSI clocks. Also add the arch_preboot_os to disable the video before enter into the kernel. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13929-4 mx7ulp: Update registers and memory map for DSI and LCDIFYe Li2017-02-16-3/+12
| | | | | | | Update the registers base address and LCDIF registers structure for mx7ulp. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13929-3 video: Update LCDIF driver to support MIPI-DSIYe Li2017-02-16-0/+44
| | | | | | | | | The LCDIF provides video source for MIPI DSI host at DPI-2 interface. When the LCDIF Framebuffer driver is enabled, it uses the panel parameters setup by environments to create a panel device and register it to DSI host driver and then enable the DSI host. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13929-2 video: Add mipi panel driver for hx8363Ye Li2017-02-16-0/+149
| | | | | | | Add the mipi dsi panel driver for device HX8363 from kernel. The panel driver needs work with mipi_dsi_northwest driver. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13929-1 video: Add MIPI DSI host controller driver for i.MX7ULPYe Li2017-02-16-0/+815
| | | | | | | | | | | | | | | Add the host driver base from kernel for MIPI DSI controller on i.MX7ULP. The controller provides a DPI-2 interface for LCDIF video stream, and a APB interface for packet transmission. The driver provides APIs to register a MIPI panel device and its driver. The panel driver can use the write packet function provided by the host driver to send control packets to panel device via APB interface. MIPI DSI has its PHY and dedicated PLL. The driver will setup them when enabling the DSI host. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13925-2 mx7ulp_arm2: Update LPDDR3/LPDDR2 script to latest versionYe Li2017-02-15-30/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Update LPDDR3 script from v1.3 to v1.5 IMX7ULP1_LPDDR3_320MHz_512MB_32bit_V1.5.inc with changes: Version 1.4 -update the precharge command to CMD=01 at DDR initializaiton phase Version 1.5 -remove unimplemented registers Write data bit delay --refer to the DDR_TRIM bits in IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn Update LPDDR2 script from v1.0 to v1.1 IMX7ULP1_LPDDR2_320MHz_1GB_32bit_V1.1.inc with changes: Version 1.1 -remove unimplemented registers Write data bit delay --refer to the DDR_TRIM bits in IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn Files: http://compass.freescale.net/livelink/livelink?func=ll&objid=235761218&objAction=browse&sort=name&viewType=1 Test: No test for ARM2 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13925-1 mx7ulp_evk: Update LPDDR3 script to V1.4Ye Li2017-02-15-18/+4
| | | | | | | | | | | | | | | | | | | Update LPDDR3 script from v1.2 to v1.4 EVK_IMX7ULP1_LPDDR3_320MHz_1GB_32bit_V1.4.inc with the changes below: Version 1.3 -Update the precharge command to CMD=01 at the DDR initialization phase Version 1.4 -remove unimplemented registers Write data bit delay --refer to the DDR_TRIM bits in IOMUXC1_DDR_SW_PAD_CTL_PAD_DDRn File: http://compass.freescale.net/livelink/livelink?func=ll&objid=235761218&objAction=browse&sort=name&viewType=1 Test: One EVK board passes overnight stress test. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13924 mx7ulp: Fix APLL num and denom setting issueYe Li2017-02-14-54/+2
| | | | | | | | | | | | For the current APLL setting, as we want the APLL PFD0 to meet DDR clock 320Mhz requirement. We set MULT to 20, NUM to 4 and DENOM to 2, to get final 22 multiplier. But according to the RM, the NUM should always be less than the DENOM. So our setting violates the rule. Actually the ROM has already set the MULT to 22 and leave NUM/DENOM in default value. The calculated APLL PFD0 clock is 318.9888Mhz, which also meet the DDR requirement. To fix the issue, we remove the PLL settings in DCD to use default value from ROM, and only set the PFD0 FRAC. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13923 mx7ulp: Fix PCC register bits mask and offset issueYe Li2017-02-14-2/+2
| | | | | | | The offset for FRAC and the mask for PCD are not correct. If we set FRAC, we can't get the right frequency. Fix them to correct value. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13899 ARM: mx7ulp: Correct the clock index on imx7ulpBai Ping2017-02-09-1/+2
| | | | | | | | On i.MX7ULP, value zero is reserved in SCG1 RCCR register, so the val should be decreased by 1 to get the correct clock source index. Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2017-02-08-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2) (cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82) (cherry picked from commit d85cd484e6825631aa1ab572e5e0539f2191d795)
* MA-9213 imx: mx7ulp-evk: Add android supportSanshan Zhang2017-01-25-0/+209
| | | | | | | | | Add android features on i.MX7ULP EVK board. Implement the code to get boot device and the serial number on mx7ulp. TODO: will add the code which check misc partition after porting BCB. Change-Id: I9d06fecba303fa4dfdcaf73da1b6246444697bba Signed-off-by: Sanshan Zhang <sanshan.zhang@nxp.com>
* MLK-13816 mx7ulp_evk/arm: Fix pad setting issue for OTG_IDYe Li2017-01-23-7/+13
| | | | | | | | The EVK and ARM2 board uses GPIOs for OTD_ID and USB_PWR. The PAD setting for OTG_ID is wrong, which should not enable output (OBE). Otherwise the device mode can't be recognized. Corret the pad settings for them. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13723 imx7d: restore epdc QoS setting after exit the lpsr modeRobby Cai2017-01-23-0/+58
| | | | | | | | without this patch, the QoS setting will be lost after exit LPSR mode. The patch moves the QoS setting into DDR setting group (in plugin mode), thus when exit LPSR mode, QoS setting will be restored as well as DDR setting. Signed-off-by: Robby Cai <robby.cai@nxp.com>
* MLK-13761 board: imx7ulp: Fix system reset after a7 rtc alarm expired.Bai Ping2017-01-20-0/+7
| | | | | | | | The board will reboot if A7 core enter mem mode by rtc, then M4 core enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode to fix this issue. Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-13782 net: fec_mxc: specify the registered eth index by dev_idAndy Duan2017-01-19-2/+9
| | | | | | Specify the registered eth index by dev_id. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13777 net: fec_mxc: avoid transfer dev_id -1 to get mac address from fuseAndy Duan2017-01-19-2/+2
| | | | | | | Avoid transfer parameter dev_id value with "-1" to .fec_get_hwaddr(), it should transfer fec->dev_id to get mac address from fuse. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13776 ocotp: Add fuse word checking before programming it on i.MX7ULPYe Li2017-01-18-0/+18
| | | | | | | | | | On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to write once, because they use ECC mode. Multiple writes may damage the ECC value and cause a wrong fuse value decoded when reading. This patch adds a checking before the fuse word programming, only can write when the word value is 0. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13749 mx7ulp_arm2: Enable MX7ULP 10x10 ARM2 board buildYe Li2017-01-12-0/+309
| | | | | | | Add the lpddr2 support from script "IMX7ULP1_LPDDR2_320MHz_1GB_32bit_V1.0.inc" and build target file for the 10x10 ARM2 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13645 mx7ulp: Modify FDT file to disable SD3.0 for mfgtoolYe Li2016-12-23-0/+40
| | | | | | | | | Since the SD3.0 kernel driver needs M4 image support, this causes problem to mfgtool. To decouple the relationship, we modify the FDT file in u-boot to disable SD3.0 when booting for mfgtool. So the kernel won't depend on M4 image. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13624 configs: imx7ulp_evk: add net args for USB NFS bootAndy Duan2016-12-16-1/+1
| | | | | | | | i.MX7ULP has no ENET controller, and kernel enable wlan0 and USB eth0 interface by default, set the net args interface to eth0 to force kernel NFS boot from USB ethernet. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13602-3 mx6ullevk/arm2: Enable module fuse checking for mx6ull boardsYe Li2016-12-14-0/+17
| | | | | | | | Enable the module disable fuse checking configurations, and ENET fuse checking during ENET setup. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Bai Ping <ping.bai@nxp.com>
* MLK-13602-2 epdc: Add disable fuse checkingYe Li2016-12-14-0/+20
| | | | | | | | Add fuse checking for EPDC module. Once the fused is programmed, the EPDC module is disabled, can't to access it. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Bai Ping <ping.bai@nxp.com>
* MLK-13602-1 mx6: Add i.MX6ULL fused modules checking supportYe Li2016-12-14-1/+44
| | | | | | | Add the modules disable fuses mapping with FDT nodes and devices name. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Bai Ping <ping.bai@nxp.com>
* MLK-13586-2 mx7d_arm2/sabresd: Update ddr3 script to V2.0 for Bank interleaveYe Li2016-12-12-109/+155
| | | | | | | | | | | | | | | | | | | | | | To improve the performance, enable the bank interleave for DDR3. Update the DDR3 settings to new script IMX7D_DDR3_533MHz_1GB_32bit_V2.0.ds Changes: 1. Enable bank interleave 2. Improve the drive strength for non-TO1.1 chips. 3. Updates ZQ_CON0 settings. 4. For 19x19 DDR3 ARM2 and 12x12 DDR3 ARM2, they are using old version scripts which were not upgrade with SABRESD script. According to DDR owner suggestion, to use same version script for all of them. File: http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1 Test: Passed stress test on one TO1.2 SABRESD, one TO1.1 SABRESD and one TO1.0 SABRESD. Passed stress test on one 12x12 ddr3 ARM2. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13586-1 mx7d_arm2: Update lpddr3 script to V2.0 for Bank interleaveYe Li2016-12-12-60/+88
| | | | | | | | | | | | | | | | | | | | To improve the performance, enable the bank interleave for LPDDR3. Update the LPDDR3 settings to new script IMX7D_LPDDR3_533MHz_2GB_32bit_V2.0.ds5. Changes: 1. Enable bank interleave 2. Improve the drive strength for non-TO1.1 chips. 3. Updates ZQ_CON0 settings. 4. Change to 0 for reserved bits. File: http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1 Test: Passed stress test on one 19x19 lpddr3 arm2 and one 12x12 lpddr3 arm2. Passed LPSR test on one 12x12 lpddr3 arm2. Signed-off-by: Ye Li <ye.li@nxp.com>
* MXSCM-237 mx6dqscm: qwks: add support for qwks rev3Juan Gutierrez2016-12-08-1/+32
| | | | | | | | | | | Support for the i.MX SX SCM QWKS rev3. The new revision has support for ov5642 camera, bluetooth and wifi support. Providing configuration files for: - Regular 1gb board - spinor Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-236 mx6dqscm: adjust some ddr calibration parametersJuan Gutierrez2016-12-08-13/+16
| | | | | | | | | | | Some adjustment to the ddr configuration like: - Precharge all commands per JEDEC - Fix the space partition values for 2Gb - Fix other values that reduce yield of scm parts per testing perfomed Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MLK-13584 configs: imx7ulp/imx6sll: enable Realtek usb-net dongle supportAndy Duan2016-12-08-0/+3
| | | | | | | | | | Enable Realtek usb-net dongle support in default for below platforms that have no Ethernet controller: - mx7ulp evk - mx6sll evk - mx6sll arm2 Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13582 net: usb: r8152: allocate cache-aligned buffer for usb transfer ↵Andy Duan2016-12-08-5/+15
| | | | | | | | buffers Transfer the cache-aligned buffer for usb transfer buffer. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13546 mx7ulp_arm2: Add validation board supportYe Li2016-12-02-0/+980
| | | | | | | | | | | | | This patch addes board level codes for MX7ULP ARM2 board. Since only 14x14 ARM2 board is ready, we only support this board. 10x10 board will support in future. eMMC/SD1/UART are ready in this patch. Other modules need board rework to test. Build target: mx7ulp_14x14_arm2_config Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13551: mx6ull: evk: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | LPDDR2 script IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc Updated to add precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13451-2: mx6ul: arm2: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | LPDDR2 script IMX6UL_LPDDR2_400MHz_16bit_V1.1.inc Updated to add precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13451-1: mx6ul: evk: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | LPDDR2 script IMX6UL_LPDDR2_400MHz_16bit_V1.1.inc Updated to add precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13540-2: mx6sx: arm2: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+6
| | | | | | | | | | | | LPDDR2 script MX6SX_19x19_LPDDR2_JEDEC.inc Updated to add Precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13540-1: mx6sx: arm2: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+6
| | | | | | | | | | | | | LPDDR2 script MX6SX_19x19_LPDDR2_JEDEC.inc Updated to add Precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13539: mx6sl: evk: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | LPDDR2 script MX6SL_MMDC_LPDDR2_register_programming_aid_v0.9.inc Updated to add Precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MXSCM-222 usb: fix swbst_mode to properly power usbJuan Gutierrez2016-12-01-1/+1
| | | | | | | | | | The definition of the SWBST_MODE_AUTO at the pfuze100_pmic.h file changed between uboot versions. On the previous version the shift to the proper bit field was part of the macro. In the uboot v2016 this macro does not include the shift and needs to be performed explicitly to properly modify the SWBST_MODE bit field. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-213: remove dmfc from boot arguments for mx6scm boardsJuan Gutierrez2016-12-01-5/+2
| | | | | | | | | | | | Intially this parameter was added to fix a video stuttering but with L4.1 the video issue is not present so we can safely get rid of this parameter. When using both ldb interfaces in separate mode and passing the dmfc argument as boot parameter to the kernel, a distortion on both displays is observed when rendering to the secondary display. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-212: mx6dqscm: usb: fix usb_otg_id iomux pad settingsJuan Gutierrez2016-12-01-0/+8
| | | | | | | | | | USB_OTG_ID iomux pad was missconfigured and not selecting the GPIO1 Alternative for QWKS and the ENET_RX_ERR for EVB, as a consequence when connecting a USB device the PWR_EN was disabled. So usb function like "usb start" was not working as it should. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MLK-13545 mx7ulp: Add HAB boot supportYe Li2016-12-01-0/+30
| | | | | | | | | | Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF size for HAB support boot on mx7ulp. Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build secure uboot. Signed-off-by: Ye Li <ye.li@nxp.com>
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