diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/DK1C20.h | 280 | ||||
| -rw-r--r-- | include/configs/DK1C20_safe_32.h | 34 | ||||
| -rw-r--r-- | include/configs/DK1C20_standard_32.h | 279 | ||||
| -rw-r--r-- | include/configs/DK1S10.h | 352 | ||||
| -rw-r--r-- | include/configs/DK1S10_mtx_ldk_20.h | 187 | ||||
| -rw-r--r-- | include/configs/DK1S10_safe_32.h | 34 | ||||
| -rw-r--r-- | include/configs/DK1S10_standard_32.h | 274 | ||||
| -rw-r--r-- | include/nios-io.h | 2 |
8 files changed, 900 insertions, 542 deletions
diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h index f357051..2d77dd7 100644 --- a/include/configs/DK1C20.h +++ b/include/configs/DK1C20.h @@ -25,264 +25,17 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * NIOS CPU configuration. +/*********************************************************************** + * Include the whole NIOS CPU configuration. * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: + * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! * - * #define CFG_NIOS_CPU_ICACHE 4096 - * #define CFG_NIOS_CPU_DCACHE 0 - * #define CFG_NIOS_CPU_OCI_BASE 0 - * #define CFG_NIOS_CPU_OCI_SIZE 0 - */ + ***********************************************************************/ #if defined(CONFIG_NIOS_SAFE_32) - -/* TODO */ - +#include <configs/DK1C20_safe_32.h> #elif defined(CONFIG_NIOS_STANDARD_32) - -/* CPU core */ -#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ -#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ -#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ -#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ -#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ -#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ -#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* on-chip extensions */ -#define CFG_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */ -#define CFG_NIOS_CPU_RAM_SIZE 0 /* size */ - -#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ -#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ -#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ - -/* timer */ -#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ - -#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ -#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ -#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ -#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ - -#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ -#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ -#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ - -#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ -#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ -#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ -#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ -#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ -#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ -#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ -#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ -#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ -#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ -#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ -#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ -#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ -#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ -#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ - -/* active serial memory i/f */ -#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */ -#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */ -#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */ - -/* memory accessibility */ -#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ -#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ - -#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ -#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ -#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ -#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: alteramac(2) */ - -/* symbolic redefinition (undef, if not present) */ -#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ -#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ - -#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ -#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ -#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ -#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ -#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ -#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ -#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ -#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ - +#include <configs/DK1C20_standard_32.h> #else #error *** CFG_ERROR: you have to setup right NIOS CPU configuration #endif @@ -419,9 +172,6 @@ #if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - /****************************************************/ - /* !!! LAN91C111 works for NIOS with patch only !!! */ - /****************************************************/ #define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ #define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) @@ -558,15 +308,15 @@ #if (CFG_NIOS_CPU_SEVENSEG_PIO == 0) -#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1) -#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2) -#error *** CFG_ERROR: status LEDs at PIO2 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3) @@ -582,27 +332,27 @@ #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4) -#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5) -#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6) -#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7) -#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8) -#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9) -#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h #else #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case diff --git a/include/configs/DK1C20_safe_32.h b/include/configs/DK1C20_safe_32.h new file mode 100644 index 0000000..a483e87 --- /dev/null +++ b/include/configs/DK1C20_safe_32.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1C20_SAFE_32_H +#define __CONFIG_DK1C20_SAFE_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1C20.h) + * + * !!! TODO !!! TODO !!! + */ +#error *** CFG_ERROR: DK1C20_safe_32 have to be defined (use DK1C20_standard_32 as template) + +#endif /* __CONFIG_DK1C20_SAFE_32_H */ diff --git a/include/configs/DK1C20_standard_32.h b/include/configs/DK1C20_standard_32.h new file mode 100644 index 0000000..ed08121 --- /dev/null +++ b/include/configs/DK1C20_standard_32.h @@ -0,0 +1,279 @@ +/* + * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1C20_STANDARD_32_H +#define __CONFIG_DK1C20_STANDARD_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1C20.h) + * + * Here we must define CPU dependencies. Any unsupported option have to + * be defined with zero, example CPU without data cache / OCI: + * + * #define CFG_NIOS_CPU_ICACHE 4096 + * #define CFG_NIOS_CPU_DCACHE 0 + * #define CFG_NIOS_CPU_OCI_BASE 0 + * #define CFG_NIOS_CPU_OCI_SIZE 0 + */ + +/* CPU core */ +#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ +#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ +#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ +#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ +#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ +#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ + /* yes(1) */ + +/* on-chip extensions */ +#define CFG_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */ +#define CFG_NIOS_CPU_RAM_SIZE 0 /* size */ + +#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ + +#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ +#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ + +/* timer */ +#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ + +#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ + /* yes(1) */ + +#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ +#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ +#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ + /* yes(1) */ + +/* serial i/o */ +#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ + +#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ +#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +/* parallel i/o */ +#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ + +#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ +#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ +#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ +#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ +#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ +#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ +#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ +#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ +#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ +#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ +#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ +#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ +#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ +#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +/* IDE i/f */ +#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ +#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ + +/* active serial memory i/f */ +#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */ +#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */ +#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */ + +/* memory accessibility */ +#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ +#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ + +#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ + +#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ + +/* LAN */ +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ + +#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ +#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ +#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ +#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ + /* cs8900(1) */ + /* ex: alteramac(2) */ + +/* symbolic redefinition (undef, if not present) */ +#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ +#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ + +#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ +#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ +#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ +#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ +#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ +#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ +#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ +#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ + +#endif /* __CONFIG_DK1C20_STANDARD_32_H */ diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h index bd7ded5..835c7a2 100644 --- a/include/configs/DK1S10.h +++ b/include/configs/DK1S10.h @@ -24,264 +24,19 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * NIOS CPU configuration. +/*********************************************************************** + * Include the whole NIOS CPU configuration. * - * Here we must define CPU dependencies. Any unsupported option have to - * be defined with zero, example CPU without data cache / OCI: + * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! * - * #define CFG_NIOS_CPU_ICACHE 4096 - * #define CFG_NIOS_CPU_DCACHE 0 - * #define CFG_NIOS_CPU_OCI_BASE 0 - * #define CFG_NIOS_CPU_OCI_SIZE 0 - */ + ***********************************************************************/ #if defined(CONFIG_NIOS_SAFE_32) - -/* TODO */ - +#include <configs/DK1S10_safe_32.h> #elif defined(CONFIG_NIOS_STANDARD_32) - -/* CPU core */ -#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ -#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ -#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ -#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ -#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ -#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ -#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ -#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ -#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ -#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ - /* yes(1) */ - -/* on-chip extensions */ -#define CFG_NIOS_CPU_RAM_BASE 0x00900000 /* on chip RAM addr */ -#define CFG_NIOS_CPU_RAM_SIZE (64 * 1024) /* 64 KB size */ - -#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ -#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ - -#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ -#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ - -/* timer */ -#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ - -#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ -#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ -#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ - /* yes(1) */ - -#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ -#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ -#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ -#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ - /* yes(1) */ - -/* serial i/o */ -#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ - -#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ -#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ -#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ -#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ -#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ -#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ - /* odd(1) */ - /* even(2) */ -#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ - /* crts(1) */ -#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ - /* yes(1) */ - -/* parallel i/o */ -#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ - -#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ -#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ -#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ -#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ -#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ -#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ -#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ -#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ -#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ -#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ -#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ -#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ -#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ -#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ -#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ -#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ -#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ - /* out(1) */ - /* in(2) */ -#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ - /* yes(1) */ -#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ - /* fall(1) */ - /* rise(2) */ - /* any(3) */ -#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ - /* level(1)*/ - /* edge(2) */ - -/* IDE i/f */ -#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ -#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ - -/* active serial memory i/f */ -#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */ -#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */ -#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */ - -/* memory accessibility */ -#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ -#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ - -#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ -#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ - -#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ -#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ - -/* LAN */ -#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ - -#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ -#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ -#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ -#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ -#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ - /* cs8900(1) */ - /* ex: alteramac(2) */ - -/* symbolic redefinition (undef, if not present) */ -#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ -#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ - -#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ -#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ -#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ -#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ -#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ -#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ -#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ -#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ - +#include <configs/DK1S10_standard_32.h> +#elif defined(CONFIG_NIOS_MTX_LDK_20) +#include <configs/DK1S10_mtx_ldk_20.h> #else #error *** CFG_ERROR: you have to setup right NIOS CPU configuration #endif @@ -308,8 +63,18 @@ #error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config #endif -#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE -#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE +#if defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE) + +#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE +#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE + +#else + +#undef CFG_SRAM_BASE +#undef CFG_SRAM_SIZE + +#endif + #define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE /*------------------------------------------------------------------------ @@ -355,7 +120,15 @@ #if (CFG_NIOS_CPU_FLASH_SIZE != 0) #define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ + +#if defined(CONFIG_NIOS_STANDARD_32) #define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */ +#elif defined(CONFIG_NIOS_MTX_LDK_20) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +#else +#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR +#endif + #define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ #define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */ @@ -388,11 +161,18 @@ * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT, * so an avalon bus timer is required. *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_TIMER_NUMS != 0) +#if (CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER) #if (CFG_NIOS_CPU_TICK_TIMER == 0) -#error *** CFG_ERROR: tick timer at TIMER0 not supported, expand your config.h +#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */ +#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ + +#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ) +#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ) +#else +#error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ +#endif #elif (CFG_NIOS_CPU_TICK_TIMER == 1) @@ -418,9 +198,6 @@ #if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */ - /****************************************************/ - /* !!! LAN91C111 works for NIOS with patch only !!! */ - /****************************************************/ #define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ #define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS) @@ -463,7 +240,7 @@ /*------------------------------------------------------------------------ * STATUS LEDs *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_PIO_NUMS != 0) +#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO) #if (CFG_NIOS_CPU_LED_PIO == 0) @@ -553,19 +330,19 @@ /*------------------------------------------------------------------------ * SEVEN SEGMENT LED DISPLAY *----------------------------------------------------------------------*/ -#if (CFG_NIOS_CPU_PIO_NUMS != 0) +#if (CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO) #if (CFG_NIOS_CPU_SEVENSEG_PIO == 0) -#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1) -#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2) -#error *** CFG_ERROR: status LEDs at PIO2 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3) @@ -581,27 +358,27 @@ #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4) -#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5) -#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6) -#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7) -#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8) -#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9) -#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h +#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h #else #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case @@ -692,17 +469,40 @@ #define CFG_MAXARGS 16 /* max number of command args*/ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +/* Default load address */ #if (CFG_SRAM_SIZE != 0) -#define CFG_LOAD_ADDR CFG_SRAM_BASE /* Default load address */ + +/* default in SRAM */ +#define CFG_LOAD_ADDR CFG_SRAM_BASE + +#elif (CFG_SDRAM_SIZE != 0) + +/* default in SDRAM */ +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) +#else +#define CFG_LOAD_ADDR CFG_SDRAM_BASE +#endif + #else -#undef CFG_LOAD_ADDR +#undef CFG_LOAD_ADDR /* force error break */ #endif + +/* MEM test area */ #if (CFG_SDRAM_SIZE != 0) -#define CFG_MEMTEST_START CFG_SDRAM_BASE /* SDRAM til stack area */ -#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */ + +/* SDRAM begin to stack area (1MB stack) */ +#if (CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE) +#define CFG_MEMTEST_START (CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE) +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) +#else +#define CFG_MEMTEST_START CFG_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) +#endif + #else -#undef CFG_MEMTEST_START +#undef CFG_MEMTEST_START /* force error break */ #undef CFG_MEMTEST_END #endif diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h new file mode 100644 index 0000000..4eb9629 --- /dev/null +++ b/include/configs/DK1S10_mtx_ldk_20.h @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1S10_MTX_LDK_20_H +#define __CONFIG_DK1S10_MTX_LDK_20_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1S10.h) + * + * Here we must define CPU dependencies. Any unsupported option have to + * be defined with zero, example CPU without data cache / OCI: + * + * #define CFG_NIOS_CPU_ICACHE 4096 + * #define CFG_NIOS_CPU_DCACHE 0 + * #define CFG_NIOS_CPU_OCI_BASE 0 + * #define CFG_NIOS_CPU_OCI_SIZE 0 + */ + +/* CPU core */ +#define CFG_NIOS_CPU_CLK 75000000 /* NIOS CPU clock */ +#define CFG_NIOS_CPU_ICACHE (0) /* instruction cache */ +#define CFG_NIOS_CPU_DCACHE (0) /* data cache */ +#define CFG_NIOS_CPU_REG_NUMS 512 /* number of register */ +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_STACK 0x02000000 /* stack top addr */ +#define CFG_NIOS_CPU_VEC_BASE 0x01000000 /* IRQ vectors addr */ +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ +#define CFG_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ + /* yes(1) */ + +/* The offset address in flash to check for the Nios signature "Ni". + * (see GM_FlashExec in germs_monitor.s) */ +#define CFG_NIOS_CPU_EXES_OFFS 0x0C + +/* on-chip extensions */ +#undef CFG_NIOS_CPU_RAM_BASE /* on chip RAM addr */ +#undef CFG_NIOS_CPU_RAM_SIZE /* 64 KB size */ + +#define CFG_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ + +#undef CFG_NIOS_CPU_OCI_BASE /* OCI core addr */ +#undef CFG_NIOS_CPU_OCI_SIZE /* size */ + +/* timer */ +#define CFG_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ + +#define CFG_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ + /* yes(1) */ + +/* serial i/o */ +#define CFG_NIOS_CPU_UART_NUMS 2 /* number of uarts */ + +#define CFG_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ +#define CFG_NIOS_CPU_UART0_IRQ 17 /* IRQ */ +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART0_SB 2 /* stop bit */ +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +#define CFG_NIOS_CPU_UART1 0x000008a0 /* UART1 addr */ +#define CFG_NIOS_CPU_UART1_IRQ 18 /* IRQ */ +#define CFG_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART1_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART1_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART1_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +/* parallel i/o */ +#define CFG_NIOS_CPU_PIO_NUMS 2 /* number of parports */ + +#define CFG_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ +#undef CFG_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO0_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO0_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO1_BITS 4 /* number of bits */ +#define CFG_NIOS_CPU_PIO1_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +/* IDE i/f */ +#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ +#define CFG_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */ +#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ + +/* memory accessibility */ +#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ +#undef CFG_NIOS_CPU_SRAM_SIZE /* 1 MB size */ + +#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ + +#define CFG_NIOS_CPU_FLASH_BASE 0x00800000 /* board Flash addr */ +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ + +/* LAN */ +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ + +#define CFG_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ +#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ +#define CFG_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ +#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ + /* cs8900(1) */ + /* ex: openmac(2) */ + /* ex: alteramac(3) */ + +/* symbolic redefinition (undef, if not present) */ +#define CFG_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ +#undef CFG_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ + +#define CFG_NIOS_CPU_CFPOWER_PIO 0 /* PIO0: CF power/sw. */ +#define CFG_NIOS_CPU_BUTTON_PIO 1 /* PIO1: buttons */ +#undef CFG_NIOS_CPU_LCD_PIO /* PIOx: ASCII LCD */ +#undef CFG_NIOS_CPU_LED_PIO /* PIOx: LED bar */ +#undef CFG_NIOS_CPU_SEVENSEG_PIO /* PIOx: 7-seg. display */ +#undef CFG_NIOS_CPU_RECONF_PIO /* PIOx: reconf pin */ +#undef CFG_NIOS_CPU_CFPRESENT_PIO /* PIOx: CF present IRQ */ +#undef CFG_NIOS_CPU_CFATASEL_PIO /* PIOx: CF ATA select */ + +#endif /* __CONFIG_DK1S10_MTX_LDK_20_H */ diff --git a/include/configs/DK1S10_safe_32.h b/include/configs/DK1S10_safe_32.h new file mode 100644 index 0000000..8541a11 --- /dev/null +++ b/include/configs/DK1S10_safe_32.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1S10_SAFE_32_H +#define __CONFIG_DK1S10_SAFE_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1S10.h) + * + * !!! TODO !!! TODO !!! + */ +#error *** CFG_ERROR: DK1S10_safe_32 have to be defined (use DK1S10_standard_32 as template) + +#endif /* __CONFIG_DK1S10_SAFE_32_H */ diff --git a/include/configs/DK1S10_standard_32.h b/include/configs/DK1S10_standard_32.h new file mode 100644 index 0000000..b83c315 --- /dev/null +++ b/include/configs/DK1S10_standard_32.h @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> + * Stephan Linz <linz@li-pro.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DK1S10_STANDARD_32_H +#define __CONFIG_DK1S10_STANDARD_32_H + +/* + * NIOS CPU configuration. (PART OF configs/DK1S10.h) + * + * Here we must define CPU dependencies. Any unsupported option have to + * be defined with zero, example CPU without data cache / OCI: + * + * #define CFG_NIOS_CPU_ICACHE 4096 + * #define CFG_NIOS_CPU_DCACHE 0 + * #define CFG_NIOS_CPU_OCI_BASE 0 + * #define CFG_NIOS_CPU_OCI_SIZE 0 + */ + +/* CPU core */ +#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ +#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ +#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ +#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ +#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ +#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ +#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ +#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ +#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ +#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ + /* yes(1) */ + +/* on-chip extensions */ +#define CFG_NIOS_CPU_RAM_BASE 0x00900000 /* on chip RAM addr */ +#define CFG_NIOS_CPU_RAM_SIZE (64 * 1024) /* 64 KB size */ + +#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ +#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ + +#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ +#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ + +/* timer */ +#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ + +#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ +#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ +#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ + /* yes(1) */ + +#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ +#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ +#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ +#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ + /* yes(1) */ + +/* serial i/o */ +#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ + +#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ +#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ +#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ +#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ +#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ +#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ + /* odd(1) */ + /* even(2) */ +#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ + /* crts(1) */ +#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ + /* yes(1) */ + +/* parallel i/o */ +#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ + +#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ +#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ +#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ +#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ +#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ +#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ +#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ +#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ +#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ +#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ +#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ +#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ +#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ +#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ +#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ +#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ +#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ + /* out(1) */ + /* in(2) */ +#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ + /* yes(1) */ +#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ + /* fall(1) */ + /* rise(2) */ + /* any(3) */ +#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ + /* level(1)*/ + /* edge(2) */ + +/* IDE i/f */ +#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ +#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ + +/* memory accessibility */ +#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ +#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ + +#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ +#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ + +#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ +#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ + +/* LAN */ +#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ + +#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ +#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ +#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ +#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ +#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ + /* cs8900(1) */ + /* ex: alteramac(2) */ + +/* symbolic redefinition (undef, if not present) */ +#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ +#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ + +#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ +#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ +#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ +#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ +#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ +#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ +#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ +#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ + +#endif /* __CONFIG_DK1S10_STANDARD_32_H */ diff --git a/include/nios-io.h b/include/nios-io.h index 64da92a..08aa9f9 100644 --- a/include/nios-io.h +++ b/include/nios-io.h @@ -117,7 +117,7 @@ typedef volatile struct nios_spi_t { unsigned status; /* Status reg */ unsigned control; /* Control reg */ unsigned reserved; /* (master only) */ - unsigned slaveselect; /* SPI slave selct mask (master only) */ + unsigned slaveselect; /* SPI slave select mask (master only) */ }nios_spi_t; /* status register */ |