diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/keymile-common.h | 62 | ||||
| -rw-r--r-- | include/configs/km_arm.h | 8 | ||||
| -rw-r--r-- | include/configs/kmeter1.h | 104 | ||||
| -rw-r--r-- | include/configs/mgcoge.h | 107 |
4 files changed, 159 insertions, 122 deletions
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index e3bd264..b934620 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008 + * (C) Copyright 2008-2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * See file CREDITS for list of people who contributed to this @@ -25,7 +25,7 @@ #define __CONFIG_KEYMILE_H /* Do boardspecific init for all boards */ -#define CONFIG_BOARD_EARLY_INIT_R 1 +#define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_BOOTCOUNT_LIMIT @@ -63,44 +63,44 @@ #define CONFIG_JFFS2_CMDLINE #define CONFIG_CMD_MTDPARTS -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ /* * Miscellaneous configurable options */ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE -#define CONFIG_HUSH_INIT_VAR 1 +#define CONFIG_HUSH_INIT_VAR #define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decr. freq: 1 ms ticks */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_LOADS_ECHO +#define CONFIG_SYS_LOADS_BAUD_CHANGE #define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */ /* @@ -108,28 +108,28 @@ * to modify in a centralized location. This is used in the HDLC * driver to set the MAC. */ -#define CONFIG_CHECK_ETHERNET_PRESENT 1 +#define CONFIG_CHECK_ETHERNET_PRESENT #define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE #define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ #define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ -#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_MAX_I2C_BUS 1 -#define CONFIG_SYS_I2C_INIT_BOARD 1 -#define CONFIG_I2C_MUX 1 +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MUX /* EEprom support */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 +#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* Support the IVM EEprom */ #define CONFIG_SYS_IVM_EEPROM_ADR 0x50 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100 -#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_PROTECTION /* * BOOTP options @@ -141,7 +141,7 @@ #define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* UBI Support for all Keymile boards */ #define CONFIG_CMD_UBI diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 533da73..b3cd5a3 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -6,6 +6,9 @@ * (C) Copyright 2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * + * (C) Copyright 2010-2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * * See file CREDITS for list of people who contributed to this * project. * @@ -25,7 +28,10 @@ * MA 02110-1301 USA */ -/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ +/* + * for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html + */ #ifndef _CONFIG_KM_ARM_H #define _CONFIG_KM_ARM_H diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index b98e6a1..a615db0 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -23,11 +23,9 @@ /* * High Level Configuration Options */ -#define CONFIG_E300 1 /* E300 family */ -#define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ -#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ -#define CONFIG_KMETER1 1 /* KMETER1 board specific */ +#define CONFIG_QE /* Has QE */ +#define CONFIG_MPC8360 /* MPC8360 CPU specific */ +#define CONFIG_KMETER1 /* KMETER1 board specific */ #define CONFIG_HOSTNAME kmeter1 #define CONFIG_SYS_TEXT_BASE 0xF0000000 @@ -42,7 +40,7 @@ "mtdparts=boot:768k(u-boot),128k(env),128k(envred)," \ "-(" CONFIG_KM_UBI_PARTITION_NAME ")" -#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MISC_INIT_R /* * System Clock Setup */ @@ -114,8 +112,9 @@ #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | \ + CSCONFIG_ODT_WR_ACS) #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_SREN) @@ -137,14 +136,14 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_50) | \ - ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ - ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - ( 3 << TIMING_CFG1_WRREC_SHIFT) | \ - ( 7 << TIMING_CFG1_REFREC_SHIFT) | \ - ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - ( 3 << TIMING_CFG1_PRETOACT_SHIFT)) +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ + (2 << TIMING_CFG1_WRTORD_SHIFT) | \ + (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ @@ -172,7 +171,7 @@ #undef CONFIG_SYS_RAMBOOT #endif -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve for Mon */ /* * Initial RAM Base Address Setup @@ -180,7 +179,8 @@ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) /* * Local Bus Configuration & Clock Setup @@ -208,7 +208,7 @@ #define CONFIG_SYS_FLASH_PROTECTION 1 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ @@ -220,8 +220,9 @@ OR_GPCM_SCY_5 | \ OR_GPCM_TRLX | OR_GPCM_EAD) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ +/* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #undef CONFIG_SYS_FLASH_CHECKSUM @@ -229,13 +230,13 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ BR_V) -#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \ +#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ OR_GPCM_TRLX | OR_GPCM_EAD) @@ -243,7 +244,7 @@ /* * PAXE on the local bus CS3 */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ @@ -267,8 +268,8 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) /* Pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP #define CONFIG_OF_STDOUT_VIA_ALIAS /* @@ -278,7 +279,7 @@ #undef CONFIG_PCI /* No PCI */ #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI #endif /* * QE UEC ethernet configuration @@ -291,7 +292,7 @@ #ifdef CONFIG_UEC_ETH1 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII */ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 @@ -305,17 +306,19 @@ #ifndef CONFIG_SYS_RAMBOOT #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) /* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #else /* CFG_RAMBOOT */ -#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ -#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 #endif /* CFG_RAMBOOT */ @@ -333,9 +336,9 @@ /* EEprom support */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */ #define CONFIG_SYS_DTT_MAX_TEMP 70 #define CONFIG_SYS_DTT_LOW_TEMP -30 #define CONFIG_SYS_DTT_HYSTERESIS 3 @@ -361,7 +364,7 @@ * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* * Core HID Setup @@ -375,45 +378,54 @@ * MMU Setup */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CONFIG_HIGH_BATS /* High BATs supported */ /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* IMMRBAR & PCI IO: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | \ + BATU_VP) #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* Stack in dcache: cacheable, no memory coherence */ #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* PAXE: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index f1bd32a..d0b7c65 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -29,15 +29,12 @@ * (easy to change) */ -#define CONFIG_MPC8247 1 -#define CONFIG_MPC8272_FAMILY 1 -#define CONFIG_MGCOGE 1 +#define CONFIG_MPC8247 +#define CONFIG_MGCOGE #define CONFIG_HOSTNAME mgcoge #define CONFIG_SYS_TEXT_BASE 0xFE000000 -#define CONFIG_CPM2 1 /* Has a CPM2 */ - /* include common defines/options for all Keymile boards */ #include "keymile-common.h" @@ -69,13 +66,13 @@ #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ #undef CONFIG_ETHER_NONE /* No external Ethernet */ -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI #define CONFIG_ETHER_INDEX 4 #define CONFIG_HAS_ETH0 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000 -# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) +# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) #ifndef CONFIG_8260_CLKIN #define CONFIG_8260_CLKIN 66000000 /* in Hz */ @@ -113,8 +110,9 @@ #define CONFIG_SYS_FLASH_SIZE 32 #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 3 +/* max num of sects on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 #define CONFIG_SYS_FLASH_BASE_1 0x50000000 #define CONFIG_SYS_FLASH_SIZE_1 32 @@ -130,24 +128,26 @@ #define CONFIG_SYS_RAMBOOT #endif -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384KB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (384 << 10) #define CONFIG_ENV_IS_IN_FLASH #ifdef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif /* CONFIG_ENV_IS_IN_FLASH */ -#define CONFIG_ENV_BUFFER_PRINT 1 +#define CONFIG_ENV_BUFFER_PRINT /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F @@ -159,15 +159,23 @@ #define I2C_ACTIVE (iop->pdir |= 0x00010000) #define I2C_TRISTATE (iop->pdir &= ~0x00010000) #define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ - else iop->pdat &= ~0x00010000 -#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ - else iop->pdat &= ~0x00020000 +#define I2C_SDA(bit) do { \ + if (bit) \ + iop->pdat |= 0x00010000; \ + else \ + iop->pdat &= ~0x00010000; \ + } while (0) +#define I2C_SCL(bit) do { \ + if (bit) \ + iop->pdat |= 0x00020000; \ + else \ + iop->pdat &= ~0x00020000; \ + } while (0) #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -/* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ #define CONFIG_SYS_DTT_MAX_TEMP 70 #define CONFIG_SYS_DTT_LOW_TEMP -30 #define CONFIG_SYS_DTT_HYSTERESIS 3 @@ -178,8 +186,9 @@ #define CONFIG_SYS_IMMR 0xF0000000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* Hard reset configuration word */ @@ -194,11 +203,11 @@ #define CONFIG_SYS_HRCW_SLAVE6 0 #define CONFIG_SYS_HRCW_SLAVE7 0 -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ #if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif #define CONFIG_SYS_HID0_INIT 0 @@ -211,14 +220,16 @@ #define CONFIG_SYS_BCR 0x10000000 #define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) -/*----------------------------------------------------------------------- +/* + *----------------------------------------------------------------------- * RMR - Reset Mode Register 5-5 *----------------------------------------------------------------------- * turn on Checkstop Reset Enable */ #define CONFIG_SYS_RMR 0 -/*----------------------------------------------------------------------- +/* + *----------------------------------------------------------------------- * TMCNTSC - Time Counter Status and Control 4-40 *----------------------------------------------------------------------- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, @@ -226,7 +237,8 @@ */ #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) -/*----------------------------------------------------------------------- +/* + *----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 4-42 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable @@ -234,7 +246,8 @@ */ #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) -/*----------------------------------------------------------------------- +/* + *----------------------------------------------------------------------- * RCCR - RISC Controller Configuration 13-7 *----------------------------------------------------------------------- */ @@ -265,14 +278,16 @@ ORxG_TRLX ) -/* Bank 1 - 60x bus SDRAM +/* + * Bank 1 - 60x bus SDRAM */ #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ +#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) #define CONFIG_SYS_MPTPR 0x1800 -/*----------------------------------------------------------------------------- +/* + *----------------------------------------------------------------------------- * Address for Mode Register Set (MRS) command *----------------------------------------------------------------------------- */ @@ -286,8 +301,9 @@ #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 -/* SDRAM initialization values -*/ +/* + * SDRAM initialization values + */ #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_8 |\ @@ -304,8 +320,9 @@ PSDMR_WRC_1C |\ PSDMR_CL_2) -/* GPIO/PIGGY on CS3 initialization values -*/ +/* + * GPIO/PIGGY on CS3 initialization values + */ #define CONFIG_SYS_PIGGY_BASE 0x30000000 #define CONFIG_SYS_PIGGY_SIZE 128 @@ -316,8 +333,9 @@ ORxG_CSNT | ORxG_ACS_DIV2 |\ ORxG_SCY_3_CLK | ORxG_TRLX ) -/* Board FPGA on CS4 initialization values -*/ +/* + * Board FPGA on CS4 initialization values + */ #define CONFIG_SYS_FPGA_BASE 0x40000000 #define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ @@ -328,8 +346,9 @@ ORxG_CSNT | ORxG_ACS_DIV2 |\ ORxG_SCY_3_CLK | ORxG_TRLX ) -/* CFG-Flash on CS5 initialization values -*/ +/* + * CFG-Flash on CS5 initialization values + */ #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) @@ -338,12 +357,12 @@ ORxG_CSNT | ORxG_ACS_DIV2 |\ ORxG_SCY_5_CLK | ORxG_TRLX ) -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ +#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ /* pass open firmware flat tree */ -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_FIT +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" |