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-rw-r--r--include/405_mal.h10
-rw-r--r--include/asm-ppc/mmu.h41
-rw-r--r--include/asm-ppc/processor.h2
-rw-r--r--include/bmp_logo.h1948
-rw-r--r--include/common.h9
-rw-r--r--include/commproc.h12
-rw-r--r--include/configs/CPU87.h24
-rw-r--r--include/configs/TB5200.h507
-rw-r--r--include/configs/TQM5200.h176
-rw-r--r--include/configs/TQM85xx.h18
-rw-r--r--include/configs/TQM885D.h492
-rw-r--r--include/configs/aev.h5
-rw-r--r--include/configs/bamboo.h16
-rw-r--r--include/configs/gth2.h56
-rw-r--r--include/configs/kvme080.h262
-rw-r--r--include/configs/mcc200.h62
-rw-r--r--include/configs/ppmc7xx.h70
-rw-r--r--include/configs/sbc2410x.h239
-rw-r--r--include/configs/spc1920.h362
-rw-r--r--include/configs/spieval.h7
-rw-r--r--include/configs/trab.h2
-rw-r--r--include/configs/xm250.h6
-rw-r--r--include/configs/yucca.h526
-rw-r--r--include/galileo/core.h3
-rw-r--r--include/linux/mtd/nand.h74
-rw-r--r--include/ns16550.h2
-rw-r--r--include/pcmcia.h10
-rw-r--r--include/ppc440.h1296
-rw-r--r--include/ppc4xx_enet.h26
-rw-r--r--include/usb.h1
-rw-r--r--include/xyzModem.h3
31 files changed, 4121 insertions, 2146 deletions
diff --git a/include/405_mal.h b/include/405_mal.h
index 69d20c9..0598586 100644
--- a/include/405_mal.h
+++ b/include/405_mal.h
@@ -92,11 +92,21 @@
#define MAL_ESR_PBEI 0x00000001
/* ^^ ^^ */
/* Mal IER */
+#ifdef CONFIG_440SPE
+#define MAL_IER_PT 0x00000080
+#define MAL_IER_PRE 0x00000040
+#define MAL_IER_PWE 0x00000020
+#define MAL_IER_DE 0x00000010
+#define MAL_IER_OTE 0x00000004
+#define MAL_IER_OE 0x00000002
+#define MAL_IER_PE 0x00000001
+#else
#define MAL_IER_DE 0x00000010
#define MAL_IER_NE 0x00000008
#define MAL_IER_TE 0x00000004
#define MAL_IER_OPBE 0x00000002
#define MAL_IER_PLBE 0x00000001
+#endif
/* MAL Channel Active Set and Reset Registers */
#define MAL_TXRX_CASR (0x80000000)
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 2606b79..baaf6f7 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -470,4 +470,45 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
+#ifdef CONFIG_440SPE
+/*----------------------------------------------------------------------------+
+| Following instructions are not available in Book E mode of the GNU assembler.
++----------------------------------------------------------------------------*/
+#define DCCCI(ra,rb) .long 0x7c000000|\
+ (ra<<16)|(rb<<11)|(454<<1)
+
+#define ICCCI(ra,rb) .long 0x7c000000|\
+ (ra<<16)|(rb<<11)|(966<<1)
+
+#define DCREAD(rt,ra,rb) .long 0x7c000000|\
+ (rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
+
+#define ICREAD(ra,rb) .long 0x7c000000|\
+ (ra<<16)|(rb<<11)|(998<<1)
+
+#define TLBSX(rt,ra,rb) .long 0x7c000000|\
+ (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
+
+#define TLBWE(rs,ra,ws) .long 0x7c000000|\
+ (rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
+
+#define TLBRE(rt,ra,ws) .long 0x7c000000|\
+ (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
+
+#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\
+ (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
+
+#define MSYNC .long 0x7c000000|\
+ (598<<1)
+
+#define MBAR_INST .long 0x7c000000|\
+ (854<<1)
+
+/*----------------------------------------------------------------------------+
+| Following instruction is not available in PPC405 mode of the GNU assembler.
++----------------------------------------------------------------------------*/
+#define TLBRE(rt,ra,ws) .long 0x7c000000|\
+ (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
+
+#endif
#endif /* _PPC_MMU_H_ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 9ff03af..44b23f1 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -735,6 +735,8 @@
#define PVR_405EP_RB 0x51210950
#define PVR_440SP_RA 0x53221850
#define PVR_440SP_RB 0x53221891
+#define PVR_440SPe_RA 0x53421890
+#define PVR_440SPe_RB 0x53421891
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000
diff --git a/include/bmp_logo.h b/include/bmp_logo.h
deleted file mode 100644
index 9c924b8..0000000
--- a/include/bmp_logo.h
+++ /dev/null
@@ -1,1948 +0,0 @@
-/*
- * Automatically generated by "tools/bmp_logo"
- *
- * DO NOT EDIT
- *
- */
-
-
-#ifndef __BMP_LOGO_H__
-#define __BMP_LOGO_H__
-
-#define BMP_LOGO_WIDTH 160
-#define BMP_LOGO_HEIGHT 96
-#define BMP_LOGO_COLORS 31
-#define BMP_LOGO_OFFSET 16
-
-unsigned short bmp_logo_palette[] = {
- 0x0343, 0x0454, 0x0565, 0x0565, 0x0676, 0x0787, 0x0898, 0x0999,
- 0x0AAA, 0x0ABA, 0x0BCB, 0x0CCC, 0x0DDD, 0x0EEE, 0x0FFF, 0x0FB3,
- 0x0FB4, 0x0FC4, 0x0FC5, 0x0FC6, 0x0FD7, 0x0FD8, 0x0FD9, 0x0FDA,
- 0x0FEA, 0x0FEB, 0x0FEC, 0x0FFD, 0x0FFE, 0x0FFF, 0x0FFF,
-};
-
-unsigned char bmp_logo_bitmap[] = {
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B,
- 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
- 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
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- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x1A, 0x10, 0x19, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x11, 0x10, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x11, 0x14,
- 0x10, 0x10, 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
- 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x10,
- 0x10, 0x14, 0x13, 0x10, 0x10, 0x10, 0x2E, 0x2E,
-
-};
-
-#endif /* __BMP_LOGO_H__ */
diff --git a/include/common.h b/include/common.h
index 5d8b156..e4637ad 100644
--- a/include/common.h
+++ b/include/common.h
@@ -116,12 +116,13 @@ typedef void (interrupt_handler_t)(void *);
/*
* enable common handling for all TQM8xxL/M boards:
- * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards
+ * - CONFIG_TQM8xxM will be defined for all TQM8xxM and TQM885D boards
* - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards
*/
#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
- defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M)
+ defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) || \
+ defined(CONFIG_TQM885D)
# ifndef CONFIG_TQM8xxM
# define CONFIG_TQM8xxM
# endif
@@ -458,6 +459,10 @@ void get_sys_info ( sys_info_t * );
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
typedef PPC440_SYS_INFO sys_info_t;
+# if defined(CONFIG_440SPE)
+ unsigned long determine_sysper(void);
+ unsigned long determine_pci_clock_per(void);
+# endif
# else
typedef PPC405_SYS_INFO sys_info_t;
# endif
diff --git a/include/commproc.h b/include/commproc.h
index 061468e..12400e3 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -1405,15 +1405,16 @@ typedef struct scc_enet {
#endif /* CONFIG_SXNI855T */
-/*** MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI *******************/
+/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
- defined(CONFIG_ETX094) || defined(CONFIG_RRVISION)|| \
- defined(CONFIG_VIRTLAB2)|| \
+ defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \
+ defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \
(defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
+
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
@@ -1438,6 +1439,11 @@ typedef struct scc_enet {
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002600)
+
+# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
+#define FEC_ENET
+# endif /* CONFIG_FEC_ENET */
+
#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 9a98e5c..7a1dada 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -455,7 +455,7 @@
#define CFG_MIN_AM_MASK 0xC0000000
/*
- * we use the same values for 32 MB and 128 MB SDRAM
+ * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
* refresh rate = 7.68 uS (100 MHz Bus Clock)
*/
@@ -510,6 +510,24 @@
PSDMR_WRC_1C |\
PSDMR_CL_2)
+ /* SDRAM initialization values for 10-column chips
+ */
+#define CFG_OR2_10COL (CFG_MIN_AM_MASK |\
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI1_A4 |\
+ ORxS_NUMR_13)
+
+#define CFG_PSDMR_10COL (PSDMR_PBI |\
+ PSDMR_SDAM_A17_IS_A5 |\
+ PSDMR_BSMA_A13_A15 |\
+ PSDMR_SDA10_PBI1_A6 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_2W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
+
/*
* Init Memory Controller:
*
@@ -588,9 +606,9 @@
BRx_MS_SDRAM_P |\
BRx_V)
-#define CFG_OR2_PRELIM CFG_OR2_9COL
+#define CFG_OR2_PRELIM CFG_OR2_8COL
-#define CFG_PSDMR CFG_PSDMR_9COL
+#define CFG_PSDMR CFG_PSDMR_8COL
#endif /* CFG_RAMBOOT */
/* Bank 3 - Dual Ported SRAM
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
new file mode 100644
index 0000000..8a6e5a6
--- /dev/null
+++ b/include/configs/TB5200.h
@@ -0,0 +1,507 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
+#define CONFIG_TB5200 1 /* ... on a TB5200 base board */
+
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
+#define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */
+#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Video console
+ */
+#if 1
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CFG_CONSOLE_IS_IN_ENV
+#endif
+
+#ifdef CONFIG_VIDEO
+#define ADD_BMP_CMD CFG_CMD_BMP
+#else
+#define ADD_BMP_CMD 0
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/* IDE */
+#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ ADD_BMP_CMD | \
+ ADD_IDE_CMD | \
+ ADD_PCI_CMD | \
+ ADD_USB_CMD | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_MII | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PING | \
+ CFG_CMD_POST_DIAG | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SNTP | \
+ CFG_CMD_BSP)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_TIMESTAMP /* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000) /* Boot low */
+# define CFG_LOWBOOT 1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#if defined(CONFIG_TQM5200_B)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "bootfile=/tftpboot/tqm5200/uImage\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
+ "update=protect off FC000000 FC07FFFF;" \
+ "erase FC000000 FC07FFFF;" \
+ "cp.b 200000 FC000000 ${filesize};" \
+ "protect on FC000000 FC07FFFF\0" \
+ ""
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "bootfile=/tftpboot/tqm5200/uImage\0" \
+ "load=tftp 200000 $(u-boot)\0" \
+ "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
+ "update=protect off FC000000 FC05FFFF;" \
+ "erase FC000000 FC05FFFF;" \
+ "cp.b 200000 FC000000 ${filesize};" \
+ "protect on FC000000 FC05FFFF\0" \
+ ""
+#endif /* CONFIG_TQM5200_B */
+
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_MODULE 2 /* Select I2C module #2 */
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/* List of I2C addresses to be verified by POST */
+#undef I2C_ADDR_LIST
+#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
+ CFG_I2C_RTC_ADDR, \
+ CFG_I2C_SLAVE }
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else /* CFG_LOWBOOT */
+#if defined(CONFIG_TQM5200_B)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000)
+#else
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
+#endif /* CONFIG_TQM5200_B */
+#endif /* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
+ (= chip selects) */
+
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM5200-0"
+#if defined(CONFIG_TQM5200_B)
+#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
+ "1280k(kernel)," \
+ "2m(initrd)," \
+ "4m(small-fs)," \
+ "16m(big-fs)," \
+ "8m(misc)"
+#else
+#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
+ "1408k(kernel)," \
+ "2m(initrd)," \
+ "4m(small-fs)," \
+ "16m(big-fs)," \
+ "8m(misc)"
+#endif /* CONFIG_TQM5200_B */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x10000
+#if defined(CONFIG_TQM5200_B)
+#define CFG_ENV_SECT_SIZE 0x40000
+#else
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#endif /* CONFIG_TQM5200_B */
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT 1
+#endif
+
+#if defined(CONFIG_TQM5200_B)
+#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
+#else
+#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#endif /* CONFIG_TQM5200_B */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR 0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ * Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ * Use for REV200 STK52XX boards. Do not use with REV100 modules
+ * (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ * 000 -> All PSC2 pins are GIOPs
+ * 001 -> CAN1/2 on PSC2 pins
+ * Use for REV100 STK52xx boards
+ * use PSC3: Bits 20:23 (mask: 0x00000300):
+ * 0001 -> USB2
+ * 0000 -> GPIO
+ * use PSC6:
+ * on STK52xx:
+ * use as UART. Pins PSC6_0 to PSC6_3 are used.
+ * Bits 9:11 (mask: 0x00700000):
+ * 101 -> PSC6 : Extended POST test is not available
+ * on MINI-FAP and TQM5200_IB:
+ * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ * 000 -> PSC6 could not be used as UART, CODEC or IrDA
+ * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ * tests.
+ */
+#define CFG_GPS_PORT_CONFIG 0x81500114
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_M41T11 1
+#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
+ year */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+#else
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
+#endif
+
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#define CFG_CS2_START 0xE5000000
+#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
+#define CFG_CS2_CFG 0x0004D930
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#define SM501_FB_BASE 0xE0000000
+#define CFG_CS1_START (SM501_FB_BASE)
+#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
+#define CFG_CS1_CFG 0x8F48FF70
+#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
+
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
+
+#define CFG_RESET_ADDRESS 0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK 0x0001BBBB
+#define CONFIG_USB_CONFIG 0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET (0x005C)
+
+/* Interval between registers */
+#define CFG_ATA_STRIDE 4
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 6b8759f..be83b67 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -2,7 +2,7 @@
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 2004-2005
+ * (C) Copyright 2004-2006
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
@@ -32,27 +32,30 @@
* (easy to change)
*/
-#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
-#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
-#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
-#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
-#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
+#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
-#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+#ifndef CONFIG_CAM5200 /* On a Cameron board or ... */
+#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
+#endif
+
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Serial console configuration
*/
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifdef CONFIG_STK52XX
@@ -96,7 +99,7 @@
/*
* Video console
*/
-#if 1
+#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SM501
#define CONFIG_VIDEO_SM501_32BPP
@@ -129,10 +132,12 @@
#define ADD_USB_CMD 0
#endif
+#ifndef CONFIG_CAM5200
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_I2C)
+#endif
#ifdef CONFIG_POST
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
@@ -176,8 +181,8 @@
#define CONFIG_TIMESTAMP /* display image timestamps */
-#if (TEXT_BASE == 0xFC000000) /* Boot low */
-# define CFG_LOWBOOT 1
+#if (TEXT_BASE != 0xFFF00000)
+# define CFG_LOWBOOT 1 /* Boot low */
#endif
/*
@@ -186,11 +191,43 @@
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
- "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
+#ifdef CONFIG_STK52XX
+# if defined(CONFIG_TQM5200_B)
+# if defined(CFG_LOWBOOT)
+# define ENV_UPDT \
+ "update=protect off FC000000 FC07FFFF;" \
+ "erase FC000000 FC07FFFF;" \
+ "cp.b 200000 FC000000 ${filesize};" \
+ "protect on FC000000 FC07FFFF\0"
+# else /* highboot */
+# define ENV_UPDT \
+ "update=protect off FFF00000 FFF7FFFF;" \
+ "erase FFF00000 FFF7FFFF;" \
+ "cp.b 200000 FFF00000 ${filesize};" \
+ "protect on FFF00000 FFF7FFFF\0"
+# endif /* CFG_LOWBOOT */
+# else /* !CONFIG_TQM5200_B */
+# define ENV_UPDT \
+ "update=protect off FC000000 FC05FFFF;" \
+ "erase FC000000 FC05FFFF;" \
+ "cp.b 200000 FC000000 ${filesize};" \
+ "protect on FC000000 FC05FFFF\0"
+# endif /* CONFIG_TQM5200_B */
+#elif defined (CONFIG_CAM5200)
+# define ENV_UPDT \
+ "update=protect off FC000000 FC03FFFF;" \
+ "erase FC000000 FC03FFFF;" \
+ "cp.b 200000 FC000000 ${filesize};" \
+ "protect on FC000000 FC03FFFF\0"
+#else
+# error "Unknown Carrier Board"
+#endif /* CONFIG_STK52XX */
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
@@ -200,18 +237,18 @@
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
- "flash_self=run ramargs addip;" \
+ "addcons=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate}\0" \
+ "flash_self=run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "flash_nfs=run nfsargs addip;" \
+ "flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
+ "bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
- "load=tftp 200000 ${u-boot}\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
- "update=protect off FC000000 FC05FFFF;" \
- "erase FC000000 FC05FFFF;" \
- "cp.b 200000 FC000000 ${filesize};" \
- "protect on FC000000 FC05FFFF\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ ENV_UPDT \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
@@ -283,45 +320,80 @@
/*
* Flash configuration
*/
-#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
+#define CFG_FLASH_BASE 0xFC000000
-/* use CFI flash driver if no module variant is spezified */
+/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
-#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+#if defined (CONFIG_CAM5200)
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
+#elif defined(CONFIG_TQM5200_B)
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000)
+#else
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
+#endif
-#if !defined(CFG_LOWBOOT)
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
-#else /* CFG_LOWBOOT */
-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
-#endif /* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
-#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
/* Dynamic MTD partition support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM5200-0"
-#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
+
+#ifdef CONFIG_STK52XX
+# if defined(CONFIG_TQM5200_B)
+# if defined(CFG_LOWBOOT)
+# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \
+ "1536k(kernel)," \
+ "3584k(small-fs)," \
+ "2m(initrd)," \
+ "8m(misc)," \
+ "16m(big-fs)"
+# else /* highboot */
+# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:2560k(kernel)," \
+ "3584k(small-fs)," \
+ "2m(initrd)," \
+ "8m(misc)," \
+ "15m(big-fs)," \
+ "1m(firmware)"
+# endif /* CFG_LOWBOOT */
+# else /* !CONFIG_TQM5200_B */
+# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
"1408k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
- "16m(big-fs)," \
- "8m(misc)"
+ "8m(misc)," \
+ "16m(big-fs)"
+# endif /* CONFIG_TQM5200_B */
+#elif defined (CONFIG_CAM5200)
+# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
+ "1792k(kernel)," \
+ "3584k(small-fs)," \
+ "2m(initrd)," \
+ "8m(misc)," \
+ "16m(big-fs)"
+#else
+# error "Unknown Carrier Board"
+#endif /* CONFIG_STK52XX */
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
+#if defined(CONFIG_TQM5200_B)
+#define CFG_ENV_SECT_SIZE 0x40000
+#else
#define CFG_ENV_SECT_SIZE 0x20000
+#endif /* CONFIG_TQM5200_B */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
-#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* Memory map
@@ -349,8 +421,15 @@
# define CFG_RAMBOOT 1
#endif
-#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
-#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
+#if defined (CONFIG_CAM5200)
+# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#elif defined(CONFIG_TQM5200_B)
+# define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
+#else
+# define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#endif
+
+#define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
@@ -411,6 +490,8 @@
#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
# define CONFIG_RTC_M41T11 1
# define CFG_I2C_RTC_ADDR 0x68
+# define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
+ year */
#else
# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
#endif
@@ -420,6 +501,10 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
+#define CFG_PROMPT_HUSH_PS2 "> "
+
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
@@ -466,32 +551,25 @@
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
-/* automatic configuration of chip selects */
-#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
-#endif
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
-#if defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START 0xE5000000
#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
#define CFG_CS2_CFG 0x0004D930
-#endif
/*
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
-#if defined (CONFIG_CS_AUTOCONF)
#define SM501_FB_BASE 0xE0000000
#define CFG_CS1_START (SM501_FB_BASE)
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
#define CFG_CS1_CFG 0x8F48FF70
#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
-#endif
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index da6946b..780f274 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -158,7 +158,7 @@
#undef CONFIG_CONS_NONE /* define if console on something else */
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-#else
+#else /* ! TQM8560 */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
@@ -170,19 +170,21 @@
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
-#endif /* CONFIG_TQM8560 */
-
-#define CONFIG_BAUDRATE 115200
-
-#define CFG_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
/* PS/2 Keyboard */
+#if !defined(CONFIG_TQM8560)
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
#define CONFIG_BOARD_EARLY_INIT_R 1
+#endif /* !CONFIG_TQM8560 */
+
+#endif /* CONFIG_TQM8560 */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
new file mode 100644
index 0000000..ede4e3b
--- /dev/null
+++ b/include/configs/TQM885D.h
@@ -0,0 +1,492 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2006
+ * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
+#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
+
+#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
+#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
+#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
+#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */
+ /* (it will be used if there is no */
+ /* 'cpuclk' variable with valid value) */
+
+#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */
+ /* (function measure_gclk() */
+ /* will be called) */
+#ifdef CFG_MEASURE_CPUCLK
+#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
+#endif
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+
+#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_BOARD_TYPES 1 /* support board types */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "rootpath=/opt/eldk/ppc_8xx\0" \
+ "bootfile=/tftpboot/TQM866M/uImage\0" \
+ "kernel_addr=40080000\0" \
+ "ramdisk_addr=40180000\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+
+#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
+
+/* enable I2C and select the hardware/software driver */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+
+#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
+#define CFG_I2C_SLAVE 0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL 0x00000020 /* PB 26 */
+#define PB_SDA 0x00000010 /* PB 27 */
+
+#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
+#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
+#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+# define CONFIG_RTC_DS1337 1
+# define CFG_I2C_RTC_ADDR 0x68
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
+
+#define CONFIG_TIMESTAMP /* but print image timestmps */
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
+ CFG_CMD_MII | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PING )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if 0
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
+#endif
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
+#define CFG_ALT_MEMTEST /* alternate, more extensive
+ memory test.*/
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x40000000
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
+#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
+#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else /* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif /* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR (0xEC000000)
+#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+
+/*
+ * FLASH timing: Default value of OR0 after reset
+ */
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
+ OR_SCY_6_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP CFG_OR0_REMAP
+#define CFG_OR1_PRELIM CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
+#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
+#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
+#define CFG_OR_TIMING_SDRAM 0x00000A00
+
+#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_OR3_PRELIM CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
+#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
+#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
+ BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif /* CONFIG_CAN_DRIVER */
+
+/*
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4 Number of refresh cycles per period
+ * 64 Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
+
+/*
+ * Memory Periodic Timer Prescaler
+ * Periodic timer for refresh, start with refresh rate for 40 MHz clock
+ * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
+ */
+#define CFG_MAMR_PTA 39
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
+ * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+/* 10 column SDRAM */
+#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Network configuration
+ */
+#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
+#define CONFIG_FEC_ENET /* enable ethernet on FEC */
+#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
+#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#define CFG_DISCOVER_PHY
+#endif
+
+#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
+ switching to another netwok (if the
+ tried network is unreachable) */
+
+#define CONFIG_ETHPRIME "SCC ETHERNET"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/aev.h b/include/configs/aev.h
index aa6bc91..8d9f0a1 100644
--- a/include/configs/aev.h
+++ b/include/configs/aev.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2003-2005
+ * (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2005
@@ -370,10 +370,7 @@
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
-/* automatic configuration of chip selects */
-#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
-#endif
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 6d32821..2c1c319 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -49,7 +49,7 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
@@ -257,8 +257,8 @@
"kernel_addr=fff00000\0" \
"ramdisk_addr=fff10000\0" \
"load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \
- "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
- "cp.b 100000 fff80000 80000;" \
+ "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
+ "cp.b 100000 fffa0000 60000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
@@ -358,6 +358,14 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING
+
+#ifdef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#else
+#define CONFIG_AUTO_COMPLETE
+#endif
+
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/gth2.h b/include/configs/gth2.h
index 77d2d56..a49ed3b 100644
--- a/include/configs/gth2.h
+++ b/include/configs/gth2.h
@@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -34,7 +34,7 @@
#define CONFIG_AU1000 1
-#define CONFIG_MISC_INIT_R 1
+#define CONFIG_MISC_INIT_R 1
#define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */
@@ -59,21 +59,21 @@
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_BOOTARGS "panic=1"
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#define CONFIG_BOOTARGS "panic=1"
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CONFIG_EXTRA_ENV_SETTINGS \
"addmisc=setenv bootargs $(bootargs) " \
- "ethaddr=$(ethaddr) \0" \
- "netboot=bootp;run addmisc;bootm\0" \
- ""
+ "ethaddr=$(ethaddr) \0" \
+ "netboot=bootp;run addmisc;bootm\0" \
+ ""
/* Boot from Compact flash partition 2 as default */
#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm"
-#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
- CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \
+ CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \
CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT ))
#include <cmd_confdefs.h>
@@ -81,11 +81,11 @@
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "GTH2 # " /* Monitor Command Prompt */
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args*/
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "GTH2 # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args*/
#define CFG_MALLOC_LEN 128*1024
@@ -93,16 +93,16 @@
#define CFG_MHZ 500
-#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
+#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
-#define CFG_LOAD_ADDR 0x81000000 /* default load address */
+#define CFG_LOAD_ADDR 0x81000000 /* default load address */
#define CFG_MEMTEST_START 0x80100000
#define CFG_MEMTEST_END 0x83000000
-#define CONFIG_HW_WATCHDOG 1
+#define CONFIG_HW_WATCHDOG 1
/*-----------------------------------------------------------------------
* FLASH and environment organization
@@ -113,8 +113,8 @@
#define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */
/* The following #defines are needed to get flash environment right */
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (192 << 10)
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (192 << 10)
#define CFG_INIT_SP_OFFSET 0x400000
@@ -125,7 +125,7 @@
#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
-#define CFG_ENV_IS_NOWHERE 1
+#define CFG_ENV_IS_NOWHERE 1
/* Address and size of Primary Environment Sector */
#define CFG_ENV_ADDR 0xB0030000
@@ -158,21 +158,21 @@
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CFG_ATA_IDE0_OFFSET 0
-#define CFG_ATA_BASE_ADDR CFG_PCMCIA_IO_BASE
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_IO_BASE
/* Offset for data I/O */
-#define CFG_ATA_DATA_OFFSET 0
+#define CFG_ATA_DATA_OFFSET 0
-/* Offset for normal register accesses */
-#define CFG_ATA_REG_OFFSET 0
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET 0
-/* Offset for alternate registers */
-#define CFG_ATA_ALT_OFFSET 0x0200
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0200
/*-----------------------------------------------------------------------
* Cache Configuration
diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h
new file mode 100644
index 0000000..61cf705
--- /dev/null
+++ b/include/configs/kvme080.h
@@ -0,0 +1,262 @@
+/*
+ * (C) Copyright 2005
+ * Sangmoon Kim, dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC824X 1
+#define CONFIG_MPC8245 1
+#define CONFIG_KVME080 1
+
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_IPADDR 192.168.0.2
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_SERVERIP 192.168.0.1
+
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 " \
+ "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
+ "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
+ "kvme080:eth0:none " \
+ "mtdparts=phys_mapped_flash:12m(root),-(kernel)"
+
+#define CONFIG_BOOTCOMMAND \
+ "tftp 800000 kvme080/uImage; " \
+ "bootm 800000"
+
+#define CONFIG_LOADADDR 800000
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_LOADS_ECHO 1
+#undef CFG_LOADS_BAUD_CHANGE
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_DS164x
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_CACHE | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_SNTP)
+
+#define CONFIG_NETCONSOLE
+
+#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE CFG_CBSIZE
+
+#define CFG_MEMTEST_START 0x00400000
+#define CFG_MEMTEST_END 0x07C00000
+
+#define CFG_LOAD_ADDR 0x00100000
+#define CFG_HZ 1000
+
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_GBL_DATA_SIZE 128
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x7C000000
+#define CFG_EUMB_ADDR 0xFC000000
+#define CFG_NVRAM_BASE_ADDR 0xFF000000
+#define CFG_NS16550_COM1 0xFF080000
+#define CFG_NS16550_COM2 0xFF080010
+#define CFG_NS16550_COM3 0xFF080020
+#define CFG_NS16550_COM4 0xFF080030
+#define CFG_RESET_ADDRESS 0xFFF00100
+
+#define CFG_MAX_RAM_SIZE 0x20000000
+#define CFG_FLASH_SIZE (16 * 1024 * 1024)
+#define CFG_NVRAM_SIZE 0x7FFF8
+
+#define CONFIG_VERY_BIG_RAM
+
+#define CFG_MONITOR_LEN 0x00040000
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MALLOC_LEN (512 << 10)
+
+#define CFG_BOOTMAPSZ (8 << 20)
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_USE_BUFFER_WRITE
+#define CFG_FLASH_PROTECTION
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_PROTECT_CLEAR
+
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 256
+
+#define CFG_FLASH_ERASE_TOUT 120000
+#define CFG_FLASH_WRITE_TOUT 500
+
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS 1
+
+#define CFG_ENV_IS_IN_NVRAM 1
+#define CONFIG_ENV_OVERWRITE 1
+#define CFG_NVRAM_ACCESS_ROUTINE
+#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR
+#define CFG_ENV_SIZE 0x400
+#define CFG_ENV_OFFSET 0
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK 14745600
+
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+#define CONFIG_EEPRO100_SROM_WRITE
+
+#define CFG_RX_ETH_BUFFER 8
+
+#define CONFIG_HARD_I2C 1
+#define CFG_I2C_SPEED 400000
+#define CFG_I2C_SLAVE 0x7F
+
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_SYS_CLK_FREQ 33333333
+
+#define CFG_CACHELINE_SIZE 32
+#if CONFIG_COMMANDS & CFG_CMD_KGDB
+# define CFG_CACHELINE_SHIFT 5
+#endif
+
+#define CFG_DLL_EXTEND 0x00
+#define CFG_PCI_HOLD_DEL 0x20
+
+#define CFG_ROMNAL 15
+#define CFG_ROMFAL 31
+
+#define CFG_REFINT 430
+
+#define CFG_DBUS_SIZE2 1
+
+#define CFG_BSTOPRE 121
+#define CFG_REFREC 8
+#define CFG_RDLAT 4
+#define CFG_PRETOACT 3
+#define CFG_ACTTOPRE 5
+#define CFG_ACTORW 3
+#define CFG_SDMODE_CAS_LAT 3
+#define CFG_SDMODE_WRAP 0
+
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM 1
+#define CFG_REGDIMM 0
+
+#define CFG_BANK0_START 0x00000000
+#define CFG_BANK0_END (0x4000000 - 1)
+#define CFG_BANK0_ENABLE 1
+#define CFG_BANK1_START 0x04000000
+#define CFG_BANK1_END (0x8000000 - 1)
+#define CFG_BANK1_ENABLE 1
+#define CFG_BANK2_START 0x3ff00000
+#define CFG_BANK2_END 0x3fffffff
+#define CFG_BANK2_ENABLE 0
+#define CFG_BANK3_START 0x3ff00000
+#define CFG_BANK3_END 0x3fffffff
+#define CFG_BANK3_ENABLE 0
+#define CFG_BANK4_START 0x00000000
+#define CFG_BANK4_END 0x00000000
+#define CFG_BANK4_ENABLE 0
+#define CFG_BANK5_START 0x00000000
+#define CFG_BANK5_END 0x00000000
+#define CFG_BANK5_ENABLE 0
+#define CFG_BANK6_START 0x00000000
+#define CFG_BANK6_END 0x00000000
+#define CFG_BANK6_ENABLE 0
+#define CFG_BANK7_START 0x00000000
+#define CFG_BANK7_END 0x00000000
+#define CFG_BANK7_ENABLE 0
+
+#define CFG_BANK_ENABLE 0x03
+
+#define CFG_ODCR 0x75
+#define CFG_PGMAX 0x32
+
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+#define BOOTFLAG_COLD 0x01
+#define BOOTFLAG_WARM 0x02
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index d8d63a1..ce33b85 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -47,8 +47,22 @@
/*
* Serial console configuration
+ *
+ * To select console on the one of 8 external UARTs,
+ * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
+ * or as 5, 6, 7, or 8 for the second Quad UART.
+ *
+ * CONFIG_PSC_CONSOLE must be undefined in this case.
+ */
+/* #define CONFIG_QUART_CONSOLE 1 */ /* console is on UART1 of QUART1 */
+/*
+ * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
+ * and undefine CONFIG_QUART_CONSOLE.
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
+#error "Select only one console device!"
+#endif
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
@@ -256,11 +270,59 @@
#define CFG_CS2_SIZE 0x00001000
#define CFG_CS2_CFG 0x1d300
+/* Second Quad UART @0x80010000 */
+#define CFG_CS1_START 0x80010000
+#define CFG_CS1_SIZE 0x00001000
+#define CFG_CS1_CFG 0x1d300
+
+/*
+ * Select one of quarts as a default
+ * console. If undefined - PSC console
+ * wil be default
+ */
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
#define CFG_RESET_ADDRESS 0xff000000
+/*
+ * QUART Expanders support
+ */
+#if defined(CONFIG_QUART_CONSOLE)
+/*
+ * We'll use NS16550 chip routines,
+ */
+#define CFG_NS16550 1
+#define CFG_NS16550_SERIAL 1
+#define CONFIG_CONS_INDEX 1
+/*
+ * To achieve necessary offset on SC16C554
+ * A0-A2 (register select) pins with NS16550
+ * functions (in struct NS16550), REG_SIZE
+ * should be 4, because A0-A2 pins are connected
+ * to DA2-DA4 address bus lines.
+ */
+#define CFG_NS16550_REG_SIZE 4
+/*
+ * LocalPlus Bus already inited in cpu_init_f(),
+ * so can work with QUART's chip selects.
+ * One of four SC16C554 UARTs is selected with
+ * A3-A4 (DA5-DA6) lines.
+ */
+#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5)
+#define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
+#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
+#define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
+#elif
+#error "Wrong QUART expander number."
+#endif
+
+/*
+ * SC16C554 chip's external crystal oscillator frequency
+ * is 7.3728 MHz
+ */
+#define CFG_NS16550_CLK 7372800
+#endif /* CONFIG_QUART_CONSOLE */
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h
index ea15524..072b9dd 100644
--- a/include/configs/ppmc7xx.h
+++ b/include/configs/ppmc7xx.h
@@ -1,9 +1,9 @@
/*
* ppmc7xx.h
* ---------
- *
+ *
* Wind River PPMC 7xx/74xx board configuration file.
- *
+ *
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
@@ -16,15 +16,15 @@
/*===================================================================
- *
+ *
* User configurable settings - Modify to your preference
- *
+ *
*===================================================================
*/
/*
* Debug
- *
+ *
* DEBUG - Define this is you want extra debug info
* GTREGREAD - Required to build with debug
* do_bdinfo - Required to build with debug
@@ -37,7 +37,7 @@
/*
* CPU type
- *
+ *
* CONFIG_7xx - We have a 750 or 755 CPU
* CONFIG_74xx - We have a 7400 CPU
* CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
@@ -52,11 +52,11 @@
/*
* Monitor configuration
- *
+ *
* CONFIG_COMMANDS - List of command sets to include in shell
- *
+ *
* The following command sets have been tested and known to work:
- *
+ *
* CFG_CMD_CACHE - Cache control commands
* CFG_CMD_MEMORY - Memory display, change and test commands
* CFG_CMD_FLASH - Erase and program flash
@@ -91,7 +91,7 @@
/*
* PCI config
- *
+ *
* CONFIG_PCI - Enable PCI bus
* CONFIG_PCI_PNP - Enable Plug & Play support
* CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
@@ -104,7 +104,7 @@
/*
* Network config
- *
+ *
* CONFIG_NET_MULTI - Support for multiple network interfaces
* CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
* CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
@@ -117,18 +117,18 @@
/*
* Enable extra init functions
- *
+ *
* CONFIG_MISC_INIT_F - Call pre-relocation init functions
* CONFIG_MISC_INIT_R - Call post relocation init functions
*/
#undef CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
+#define CONFIG_MISC_INIT_R
/*
* Boot config
- *
+ *
* CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
* CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
*/
@@ -142,9 +142,9 @@
/*===================================================================
- *
+ *
* Board configuration settings - You should not need to modify these
- *
+ *
*===================================================================
*/
@@ -154,9 +154,9 @@
/*
* Memory map
- *
+ *
* This board runs in a standard CHRP (Map-B) configuration.
- *
+ *
* Type Start End Size Width Chip Sel
* ----------- ----------- ----------- ------- ------- --------
* SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
@@ -164,9 +164,9 @@
* UART 0x7C000000 RCS2
* Mailbox 0xFF000000 RCS1
* Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
- *
+ *
* Flash sectors are laid out as follows.
- *
+ *
* Sector Start End Size Comments
* ------- ----------- ----------- ------- -----------
* 0 0xFFC00000 0xFFC3FFFF 256KB
@@ -193,7 +193,7 @@
/*
* SDRAM config - see memory map details above.
- *
+ *
* CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
* CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
*/
@@ -202,9 +202,9 @@
#define CFG_SDRAM_SIZE 0x04000000
-/*
+/*
* Flash config - see memory map details above.
- *
+ *
* CFG_FLASH_BASE - Start address of flash memory
* CFG_FLASH_SIZE - Total size of contiguous flash mem
* CFG_FLASH_ERASE_TOUT - Erase timeout in ms
@@ -223,7 +223,7 @@
/*
* Monitor config - see memory map details above
- *
+ *
* CFG_MONITOR_BASE - Base address of monitor code
* CFG_MALLOC_LEN - Size of malloc pool (128KB)
*/
@@ -234,7 +234,7 @@
/*
* Command shell settings
- *
+ *
* CFG_BARGSIZE - Boot Argument buffer size
* CFG_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
* CFG_CBSIZE - Console Buffer (input) size
@@ -261,10 +261,10 @@
/*
* Environment config - see memory map details above
- *
+ *
* CFG_ENV_IS_IN_FLASH - The env variables are stored in flash
* CFG_ENV_ADDR - Address of the sector containing env vars
- * CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
+ * CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
* CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
*/
@@ -282,7 +282,7 @@
* Since the main system RAM is initialised very early, we place the INIT_RAM
* in the main system RAM just above the exception vectors. The contents are
* copied to top of RAM by the init code.
- *
+ *
* CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect
* CFG_INIT_RAM_END - Size of Init RAM
* CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
@@ -297,7 +297,7 @@
/*
* Initial BAT config
- *
+ *
* BAT0 - System SDRAM
* BAT1 - LED's and Serial Port
* BAT2 - PCI Memory
@@ -327,7 +327,7 @@
/*
* Cache config
- *
+ *
* CFG_CACHELINE_SIZE - Size of a cache line (CPU specific)
* CFG_L2 - L2 cache enabled if defined
* L2_INIT - L2 cache init flags
@@ -342,7 +342,7 @@
/*
* Clocks config
- *
+ *
* CFG_BUS_HZ - Bus clock frequency in Hz
* CFG_BUS_CLK - As above (?)
* CFG_HZ - Decrementer freq in Hz
@@ -355,7 +355,7 @@
/*
* Serial port config
- *
+ *
* CFG_BAUDRATE_TABLE - List of valid baud rates
* CFG_NS16550 - Include the NS16550 driver
* CFG_NS16550_SERIAL - Include the serial (wrapper) driver
@@ -398,7 +398,7 @@
/*
* Extra init functions
- *
+ *
* CFG_BOARD_ASM_INIT - Call assembly init code
*/
@@ -407,11 +407,11 @@
/*
* Boot flags
- *
+ *
* BOOTFLAG_COLD - Indicates a power-on boot
* BOOTFLAG_WARM - Indicates a software reset
*/
-
+
#define BOOTFLAG_COLD 0x01
#define BOOTFLAG_WARM 0x02
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
new file mode 100644
index 0000000..866f7b0
--- /dev/null
+++ b/include/configs/sbc2410x.h
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * Modified for the friendly-arm SBC-2410X by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * Configuation settings for the friendly-arm SBC-2410X board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
+#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
+
+
+#define USE_920T_MMU 1
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
+#define CS8900_BASE 0x19000300
+#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */
+
+/************************************************************
+ * RTC
+ ************************************************************/
+#define CONFIG_RTC_S3C24X0 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#define CONFIG_COMMANDS \
+ (CONFIG_CMD_DFL | \
+ CFG_CMD_CACHE | \
+ /*CFG_CMD_NAND |*/ \
+ /*CFG_CMD_EEPROM |*/ \
+ /*CFG_CMD_I2C |*/ \
+ /*CFG_CMD_USB |*/ \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_DATE | \
+ CFG_CMD_PING | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ELF)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
+#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.0.69
+#define CONFIG_SERVERIP 192.168.0.1
+/*#define CONFIG_BOOTFILE "elinos-lart" */
+#define CONFIG_BOOTCOMMAND "dhcp; bootm"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x33000000 /* default load address */
+
+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
+/* it to wrap 100 times (total 1562500) to get 1 sec. */
+#define CFG_HZ 1562500
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */
+
+#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
+
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+
+#ifdef CONFIG_AMD_LV800
+#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
+#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#endif
+
+#ifdef CONFIG_AMD_LV400
+#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
+#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#endif
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+
+/*-----------------------------------------------------------------------
+ * NAND flash settings
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define NAND_WAIT_READY(nand) NF_WaitRB()
+#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
+#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
+#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
+#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
+#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
+#define WRITE_NAND(d, adr) NF_Write(d)
+#define READ_NAND(adr) NF_Read()
+/* the following functions are NOP's because S3C24X0 handles this in hardware */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
+#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_CMDLINE_EDITING
+
+#ifdef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#else
+#define CONFIG_AUTO_COMPLETE
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
new file mode 100644
index 0000000..9d3609a
--- /dev/null
+++ b/include/configs/spc1920.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
+ *
+ * Configuation settings for the SPC1920 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __H
+#define __CONFIG_H
+
+#define CONFIG_SPC1920 1 /* SPC1920 board */
+#define CONFIG_MPC885 1 /* MPC885 CPU */
+
+#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_MII
+/* #define MII_DEBUG */
+/* #define CONFIG_FEC_ENET */
+#undef CONFIG_ETHER_ON_FEC1
+#define CONFIG_ETHER_ON_FEC2
+#define FEC_ENET
+/* #define CONFIG_FEC2_PHY_NORXERR */
+/* #define CFG_DISCOVER_PHY */
+/* #define CONFIG_PHY_ADDR 0x1 */
+#define CONFIG_FEC2_PHY 1
+
+#define CONFIG_BAUDRATE 19200
+
+/* use PLD CLK4 instead of brg */
+#undef CFG_SPC1920_SMC1_CLK4
+
+#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
+#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
+#define CFG_8xx_CPUCLK_MIN 40000000
+#define CFG_8xx_CPUCLK_MAX 133000000
+
+#define CFG_RESET_ADDRESS 0xf8000000
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+
+#if 1
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "dhcp;" \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
+ "bootm"
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
+ "bootm fe080000"
+
+#undef CONFIG_BOOTARGS
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
+
+#ifndef CONFIG_COMMANDS
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_ASKENV \
+ | CFG_CMD_ECHO \
+ | CFG_CMD_IMMAP \
+ | CFG_CMD_JFFS2 \
+ | CFG_CMD_PING \
+ | CFG_CMD_DHCP \
+ | CFG_CMD_IMMAP \
+ | CFG_CMD_MII)
+ /* & ~( CFG_CMD_NET)) */
+
+
+#endif /* !CONFIG_COMMANDS */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=>" /* Monitor Command Prompt */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR 0x00100000
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
+
+#ifdef CONFIG_BZIP2
+#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
+#else
+#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
+#endif /* CONFIG_BZIP2 */
+
+#define CFG_ALLOC_DPRAM 1 /* use allocation routines */
+
+/*
+ * Flash
+ */
+/*-----------------------------------------------------------------------
+ * Flash organisation
+ */
+#define CFG_FLASH_BASE 0xFE000000
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
+#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
+
+/* Environment is in flash */
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+
+/*-----------------------------------------------------------------------
+ * I2C configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
+#define CFG_I2C_SLAVE 0x7F
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+/* #define CFG_SCCR SCCR_TBS */
+#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * DER - Debug Enable Register
+ *-----------------------------------------------------------------------
+ * Set to zero to prevent the processor from entering debug mode
+ */
+#define CFG_DER 0
+
+
+/* Because of the way the 860 starts up and assigns CS0 the entire
+ * address space, we have to set the memory controller differently.
+ * Normally, you write the option register first, and then enable the
+ * chip select by writing the base register. For CS0, you must write
+ * the base register first, followed by the option register.
+ */
+
+
+/*
+ * Init Memory Controller:
+ */
+
+/* BR0 and OR0 (FLASH) */
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+ OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+
+/*
+ * SDRAM CS1 UPMB
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE
+#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */
+
+#define CFG_PRELIM_OR1_AM 0xF0000000
+/* #define CFG_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */
+#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
+
+#define CFG_OR1_PRELIM (CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
+#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
+
+/* #define CFG_OR1_FINAL ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */
+/* #define CFG_BR1_FINAL ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
+
+#define CFG_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
+#define CFG_PTA_PER_CLK 195
+#define CFG_MBMR_PTB 195
+#define CFG_MPTPR MPTPR_PTP_DIV16
+#define CFG_MAR 0x88
+
+#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
+ MBMR_AMB_TYPE_0 | \
+ MBMR_G0CLB_A10 | \
+ MBMR_DSB_1_CYCL | \
+ MBMR_RLFB_1X | \
+ MBMR_WLFB_1X | \
+ MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
+
+#define CFG_MBMR_9COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
+ MBMR_AMB_TYPE_1 | \
+ MBMR_G0CLB_A10 | \
+ MBMR_DSB_1_CYCL | \
+ MBMR_RLFB_1X | \
+ MBMR_WLFB_1X | \
+ MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
+
+
+/* PLD CS5 */
+#define CFG_SPC1920_PLD_BASE 0x80000000
+#define CFG_PRELIM_OR5_AM 0xffff8000
+
+#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \
+ OR_CSNT_SAM | \
+ OR_ACS_DIV1 | \
+ OR_BI | \
+ OR_SCY_0_CLK | \
+ OR_TRLX)
+
+#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
+/* #define CFG_PLD_BASE 0x30000000 */
+/* #define CFG_OR5_PRELIM 0xffff1110 */
+/* #define CFG_BR5_PRELIM 0x30000401 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
index 9ebb51e..f40dde2 100644
--- a/include/configs/spieval.h
+++ b/include/configs/spieval.h
@@ -452,32 +452,25 @@
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
-/* automatic configuration of chip selects */
-#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
-#endif
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
-#if defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START 0xE5000000
#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
#define CFG_CS2_CFG 0x0004D930
-#endif
/*
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
-#if defined (CONFIG_CS_AUTOCONF)
#define SM501_FB_BASE 0xE0000000
#define CFG_CS1_START (SM501_FB_BASE)
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
#define CFG_CS1_CFG 0x8F48FF70
#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
-#endif
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
diff --git a/include/configs/trab.h b/include/configs/trab.h
index 935aca2d..ae97947 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -407,7 +407,7 @@
#endif
/* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_ERASE_TOUT (15*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_IS_IN_FLASH 1
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index 952f73b..825bfd1 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -119,9 +119,9 @@
/*
* Definitions related to passing arguments to kernel.
*/
-#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
-#undef CONFIG_INITRD_TAG /* do not send initrd params */
+#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
+#define CONFIG_INITRD_TAG 1 /* do not send initrd params */
#undef CONFIG_VFD /* do not send framebuffer setup */
/*
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
new file mode 100644
index 0000000..0e58e7e
--- /dev/null
+++ b/include/configs/yucca.h
@@ -0,0 +1,526 @@
+/*
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * 1 january 2005 Alain Saurel <asaurel@amcc.com>
+ * Adapted to current Das U-Boot source
+ ***********************************************************************/
+/************************************************************************
+ * yucca.h - configuration for AMCC 440SPe Ref (yucca)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_440 1 /* ... PPC440 family */
+#define CONFIG_440SPE 1 /* Specifc SPe support */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#undef CFG_DRAM_TEST /* Disable-takes long time */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
+#define EXTCLK_33_33 33333333
+#define EXTCLK_66_66 66666666
+#define EXTCLK_50 50000000
+#define EXTCLK_83 83333333
+
+#define CONFIG_IBM_EMAC4_V4 1
+#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
+#undef CONFIG_SHOW_BOOT_PROGRESS
+#undef CONFIG_STRESS
+#undef ENABLE_ECC
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
+#define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */
+#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
+
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */
+#define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */
+
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */
+/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */
+/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
+
+#define CFG_FPGA_BASE 0xe2000000 /* epld */
+#define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
+
+/* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM 1
+#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */
+#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_SERIAL_MULTI 1
+#undef CONFIG_UART1_CONSOLE
+
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK
+/* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses */
+#define IIC0_DIMM0_ADDR 0x53
+#define IIC0_DIMM1_ADDR 0x52
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+
+#define IIC0_BOOTPROM_ADDR 0x50
+#define IIC0_ALT_BOOTPROM_ADDR 0x54
+
+/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
+
+/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
+/* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
+#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
+/* #endif */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/* #define CFG_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
+
+#undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
+#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
+#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
+#define CONFIG_ENV_OVERWRITE 1
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=yucca\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/opt/eldk/ppc_4xx\0" \
+ "bootfile=yucca/uImage\0" \
+ "kernel_addr=E7F10000\0" \
+ "ramdisk_addr=E7F20000\0" \
+ "load=tftp 100000 yuca/u-boot.bin\0" \
+ "update=protect off 2:4-7;era 2:4-7;" \
+ "cp.b ${fileaddr} FFFB0000 ${filesize};" \
+ "setenv filesize;saveenv\0" \
+ "upd=run load;run update\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DIAG | \
+ CFG_CMD_ELF | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_MII | \
+ CFG_CMD_NET | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_PING | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_MII 1 /* MII PHY management */
+#undef CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
+#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_FLASH_ADDR0 0x5555
+#define CFG_FLASH_ADDR1 0x2aaa
+#define CFG_FLASH_WORD_SIZE unsigned char
+
+#define CFG_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */
+#define CFG_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CFG_ENV_ADDR 0xfffa0000
+/* #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
+#define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */
+#endif /* CFG_ENV_IS_IN_FLASH */
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
+#define CFG_PCI_TARGET_INIT /* let board init pci target */
+#undef CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
+/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
+
+/*
+ * NETWORK Support (PCI):
+ */
+/* Support for Intel 82557/82559/82559ER chips. */
+#define CONFIG_EEPRO100
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
+#define CFG_CACHELINE_SIZE 32 /* ... */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/* FB Divisor selection */
+#define FPGA_FB_DIV_6 6
+#define FPGA_FB_DIV_10 10
+#define FPGA_FB_DIV_12 12
+#define FPGA_FB_DIV_20 20
+
+/* VCO Divisor selection */
+#define FPGA_VCO_DIV_4 4
+#define FPGA_VCO_DIV_6 6
+#define FPGA_VCO_DIV_8 8
+#define FPGA_VCO_DIV_10 10
+
+/*----------------------------------------------------------------------------+
+| FPGA registers and bit definitions
++----------------------------------------------------------------------------*/
+/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
+/* TLB initialization makes it correspond to logical address 0xE2000000. */
+/* => Done init_chip.s in bootlib */
+#define FPGA_REG_BASE_ADDR 0xE2000000
+#define FPGA_GPIO_BASE_ADDR 0xE2010000
+#define FPGA_INT_BASE_ADDR 0xE2020000
+
+/*----------------------------------------------------------------------------+
+| Display
++----------------------------------------------------------------------------*/
+#define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR
+
+#define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06)
+#define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04)
+#define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02)
+#define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00)
+/*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
+/*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/
+
+/*----------------------------------------------------------------------------+
+| ethernet/reset/boot Register 1
++----------------------------------------------------------------------------*/
+#define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10)
+
+#define FPGA_REG10_10MHZ_ENABLE 0x8000
+#define FPGA_REG10_100MHZ_ENABLE 0x4000
+#define FPGA_REG10_GIGABIT_ENABLE 0x2000
+#define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/
+#define FPGA_REG10_RESET_ETH 0x0800
+#define FPGA_REG10_AUTO_NEG_DIS 0x0400
+#define FPGA_REG10_INTP_ETH 0x0200
+
+#define FPGA_REG10_RESET_HISR 0x0080
+#define FPGA_REG10_ENABLE_DISPLAY 0x0040
+#define FPGA_REG10_RESET_SDRAM 0x0020
+#define FPGA_REG10_OPER_BOOT 0x0010
+#define FPGA_REG10_SRAM_BOOT 0x0008
+#define FPGA_REG10_SMALL_BOOT 0x0004
+#define FPGA_REG10_FORCE_COLA 0x0002
+#define FPGA_REG10_COLA_MANUAL 0x0001
+
+#define FPGA_REG10_SDRAM_ENABLE 0x0020
+
+#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
+#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
+
+/*----------------------------------------------------------------------------+
+| MUX control
++----------------------------------------------------------------------------*/
+#define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12)
+
+#define FPGA_REG12_EBC_CTL 0x8000
+#define FPGA_REG12_UART1_CTS_RTS 0x4000
+#define FPGA_REG12_UART0_RX_ENABLE 0x2000
+#define FPGA_REG12_UART1_RX_ENABLE 0x1000
+#define FPGA_REG12_UART2_RX_ENABLE 0x0800
+#define FPGA_REG12_EBC_OUT_ENABLE 0x0400
+#define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200
+#define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100
+#define FPGA_REG12_GPIO_SELECT 0x0010
+#define FPGA_REG12_GPIO_CHREG 0x0008
+#define FPGA_REG12_GPIO_CLK_CHREG 0x0004
+#define FPGA_REG12_GPIO_OETRI 0x0002
+#define FPGA_REG12_EBC_ERROR 0x0001
+
+/*----------------------------------------------------------------------------+
+| PCI Clock control
++----------------------------------------------------------------------------*/
+#define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16)
+
+#define FPGA_REG16_PCI_CLK_CTL0 0x8000
+#define FPGA_REG16_PCI_CLK_CTL1 0x4000
+#define FPGA_REG16_PCI_CLK_CTL2 0x2000
+#define FPGA_REG16_PCI_CLK_CTL3 0x1000
+#define FPGA_REG16_PCI_CLK_CTL4 0x0800
+#define FPGA_REG16_PCI_CLK_CTL5 0x0400
+#define FPGA_REG16_PCI_CLK_CTL6 0x0200
+#define FPGA_REG16_PCI_CLK_CTL7 0x0100
+#define FPGA_REG16_PCI_CLK_CTL8 0x0080
+#define FPGA_REG16_PCI_CLK_CTL9 0x0040
+#define FPGA_REG16_PCI_EXT_ARB0 0x0020
+#define FPGA_REG16_PCI_MODE_1 0x0010
+#define FPGA_REG16_PCI_TARGET_MODE 0x0008
+#define FPGA_REG16_PCI_INTP_MODE 0x0004
+
+/* FB1 Divisor selection */
+#define FPGA_REG16_FB2_DIV_MASK 0x1000
+#define FPGA_REG16_FB2_DIV_LOW 0x0000
+#define FPGA_REG16_FB2_DIV_HIGH 0x1000
+/* FB2 Divisor selection */
+/* S3 switch on Board */
+#define FPGA_REG16_FB1_DIV_MASK 0x2000
+#define FPGA_REG16_FB1_DIV_LOW 0x0000
+#define FPGA_REG16_FB1_DIV_HIGH 0x2000
+/* PCI0 Clock Selection */
+/* S3 switch on Board */
+#define FPGA_REG16_PCI0_CLK_MASK 0x0c00
+#define FPGA_REG16_PCI0_CLK_33_33 0x0000
+#define FPGA_REG16_PCI0_CLK_66_66 0x0800
+#define FPGA_REG16_PCI0_CLK_100 0x0400
+#define FPGA_REG16_PCI0_CLK_133_33 0x0c00
+/* VCO Divisor selection */
+/* S3 switch on Board */
+#define FPGA_REG16_VCO_DIV_MASK 0xc000
+#define FPGA_REG16_VCO_DIV_4 0x0000
+#define FPGA_REG16_VCO_DIV_8 0x4000
+#define FPGA_REG16_VCO_DIV_6 0x8000
+#define FPGA_REG16_VCO_DIV_10 0xc000
+/* Master Clock Selection */
+/* S3, S4 switches on Board */
+#define FPGA_REG16_MASTER_CLK_MASK 0x01c0
+#define FPGA_REG16_MASTER_CLK_EXT 0x0000
+#define FPGA_REG16_MASTER_CLK_66_66 0x0040
+#define FPGA_REG16_MASTER_CLK_50 0x0080
+#define FPGA_REG16_MASTER_CLK_33_33 0x00c0
+#define FPGA_REG16_MASTER_CLK_25 0x0100
+
+/*----------------------------------------------------------------------------+
+| PCI Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18)
+
+#define FPGA_REG18_PCI_PRSNT1 0x8000
+#define FPGA_REG18_PCI_PRSNT2 0x4000
+#define FPGA_REG18_PCI_INTA 0x2000
+#define FPGA_REG18_PCI_SLOT0_INTP 0x1000
+#define FPGA_REG18_PCI_SLOT1_INTP 0x0800
+#define FPGA_REG18_PCI_SLOT2_INTP 0x0400
+#define FPGA_REG18_PCI_SLOT3_INTP 0x0200
+#define FPGA_REG18_PCI_PCI0_VC 0x0100
+#define FPGA_REG18_PCI_PCI0_VTH1 0x0080
+#define FPGA_REG18_PCI_PCI0_VTH2 0x0040
+#define FPGA_REG18_PCI_PCI0_VTH3 0x0020
+
+/*----------------------------------------------------------------------------+
+| PCIe Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A)
+
+#define FPGA_REG1A_PE0_GLED 0x8000
+#define FPGA_REG1A_PE1_GLED 0x4000
+#define FPGA_REG1A_PE2_GLED 0x2000
+#define FPGA_REG1A_PE0_YLED 0x1000
+#define FPGA_REG1A_PE1_YLED 0x0800
+#define FPGA_REG1A_PE2_YLED 0x0400
+#define FPGA_REG1A_PE0_PWRON 0x0200
+#define FPGA_REG1A_PE1_PWRON 0x0100
+#define FPGA_REG1A_PE2_PWRON 0x0080
+#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
+#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
+#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
+#define FPGA_REG1A_PE_SPREAD0 0x0008
+#define FPGA_REG1A_PE_SPREAD1 0x0004
+#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
+#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
+
+/*----------------------------------------------------------------------------+
+| PCIe Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C)
+
+#define FPGA_REG1C_PE0_ROOTPOINT 0x8000
+#define FPGA_REG1C_PE1_ENDPOINT 0x4000
+#define FPGA_REG1C_PE2_ENDPOINT 0x2000
+#define FPGA_REG1C_PE0_PRSNT 0x1000
+#define FPGA_REG1C_PE1_PRSNT 0x0800
+#define FPGA_REG1C_PE2_PRSNT 0x0400
+#define FPGA_REG1C_PE0_WAKE 0x0080
+#define FPGA_REG1C_PE1_WAKE 0x0040
+#define FPGA_REG1C_PE2_WAKE 0x0020
+#define FPGA_REG1C_PE0_PERST 0x0010
+#define FPGA_REG1C_PE1_PERST 0x0080
+#define FPGA_REG1C_PE2_PERST 0x0040
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+#define PERIOD_133_33MHZ 7500 /* 7,5ns */
+#define PERIOD_100_00MHZ 10000 /* 10ns */
+#define PERIOD_83_33MHZ 12000 /* 12ns */
+#define PERIOD_75_00MHZ 13333 /* 13,333ns */
+#define PERIOD_66_66MHZ 15000 /* 15ns */
+#define PERIOD_50_00MHZ 20000 /* 20ns */
+#define PERIOD_33_33MHZ 30000 /* 30ns */
+#define PERIOD_25_00MHZ 40000 /* 40ns */
+
+/*---------------------------------------------------------------------------*/
+
+#endif /* __CONFIG_H */
diff --git a/include/galileo/core.h b/include/galileo/core.h
index 0735d07..49f4dd2 100644
--- a/include/galileo/core.h
+++ b/include/galileo/core.h
@@ -110,7 +110,10 @@ extern unsigned int INTERNAL_REG_BASE_ADDR;
#define _1G 0x40000000
#define _2G 0x80000000
+#ifndef BOOL_WAS_DEFINED
+#define BOOL_WAS_DEFINED
typedef enum _bool{false,true} bool;
+#endif
/* Little to Big endian conversion macros */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index a522718..4b48564 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -2,7 +2,7 @@
* linux/include/linux/mtd/nand.h
*
* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
- * Steven J. Hill <sjhill@realitydiluted.com>
+ * Steven J. Hill <sjhill@realitydiluted.com>
* Thomas Gleixner <tglx@linutronix.de>
*
* $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
@@ -15,15 +15,15 @@
* Contains standard defines and IDs for NAND flash devices
*
* Changelog:
- * 01-31-2000 DMW Created
- * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
+ * 01-31-2000 DMW Created
+ * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
* so it can be used by other NAND flash device
* drivers. I also changed the copyright since none
* of the original contents of this file are specific
* to DoC devices. David can whack me with a baseball
* bat later if I did something naughty.
- * 10-11-2000 SJH Added private NAND flash structure for driver
- * 10-24-2000 SJH Added prototype for 'nand_scan' function
+ * 10-11-2000 SJH Added private NAND flash structure for driver
+ * 10-24-2000 SJH Added prototype for 'nand_scan' function
* 10-29-2001 TG changed nand_chip structure to support
* hardwarespecific function for accessing control lines
* 02-21-2002 TG added support for different read/write adress and
@@ -36,7 +36,7 @@
* CONFIG_MTD_NAND_ECC_JFFS2 is not set
* 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
*
- * 08-29-2002 tglx nand_chip structure: data_poi for selecting
+ * 08-29-2002 tglx nand_chip structure: data_poi for selecting
* internal / fs-driver buffer
* support for 6byte/512byte hardware ECC
* read_ecc, write_ecc extended for different oob-layout
@@ -45,8 +45,8 @@
* 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
* Split manufacturer and device ID structures
*
- * 02-08-2004 tglx added option field to nand structure for chip anomalities
- * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
+ * 02-08-2004 tglx added option field to nand structure for chip anomalities
+ * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
* update of nand_chip structure description
*/
#ifndef __LINUX_MTD_NAND_H
@@ -75,7 +75,7 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
* Constants for hardware specific CLE/ALE/NCE function
*/
/* Select the chip by setting nCE to low */
-#define NAND_CTL_SETNCE 1
+#define NAND_CTL_SETNCE 1
/* Deselect the chip by setting nCE to high */
#define NAND_CTL_CLRNCE 2
/* Select the command latch by setting CLE to high */
@@ -215,7 +215,7 @@ struct nand_chip;
#if 0
/**
* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
- * @lock: protection lock
+ * @lock: protection lock
* @active: the mtd device which holds the controller currently
*/
struct nand_hw_control {
@@ -244,20 +244,20 @@ struct nand_hw_control {
* is read from the chip status register
* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
- * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
+ * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
* @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
* @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
* be provided if a hardware ECC is available
* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
* @scan_bbt: [REPLACEABLE] function to scan bad block table
* @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
- * @eccsize: [INTERN] databytes used per ecc-calculation
- * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
+ * @eccsize: [INTERN] databytes used per ecc-calculation
+ * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
* @eccsteps: [INTERN] number of ecc calculation steps per page
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
* @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip
* @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
- * @state: [INTERN] the current state of the NAND device
+ * @state: [INTERN] the current state of the NAND device
* @page_shift: [INTERN] number of address bits in a page (column address bits)
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
@@ -284,7 +284,7 @@ struct nand_hw_control {
struct nand_chip {
void __iomem *IO_ADDR_R;
- void __iomem *IO_ADDR_W;
+ void __iomem *IO_ADDR_W;
u_char (*read_byte)(struct mtd_info *mtd);
void (*write_byte)(struct mtd_info *mtd, u_char byte);
@@ -297,12 +297,12 @@ struct nand_chip {
void (*select_chip)(struct mtd_info *mtd, int chip);
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
- void (*hwcontrol)(struct mtd_info *mtd, int cmd);
- int (*dev_ready)(struct mtd_info *mtd);
- void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
- int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
+ void (*hwcontrol)(struct mtd_info *mtd, int cmd);
+ int (*dev_ready)(struct mtd_info *mtd);
+ void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
+ int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
- int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
+ int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
void (*enable_hwecc)(struct mtd_info *mtd, int mode);
void (*erase_cmd)(struct mtd_info *mtd, int page);
int (*scan_bbt)(struct mtd_info *mtd);
@@ -310,17 +310,17 @@ struct nand_chip {
int eccsize;
int eccbytes;
int eccsteps;
- int chip_delay;
+ int chip_delay;
#if 0
spinlock_t chip_lock;
wait_queue_head_t wq;
- nand_state_t state;
+ nand_state_t state;
#endif
- int page_shift;
+ int page_shift;
int phys_erase_shift;
int bbt_erase_shift;
int chip_shift;
- u_char *data_buf;
+ u_char *data_buf;
u_char *oob_buf;
int oobdirty;
u_char *data_poi;
@@ -335,7 +335,7 @@ struct nand_chip {
struct nand_bbt_descr *bbt_td;
struct nand_bbt_descr *bbt_md;
struct nand_bbt_descr *badblock_pattern;
- struct nand_hw_control *controller;
+ struct nand_hw_control *controller;
void *priv;
};
@@ -352,14 +352,14 @@ struct nand_chip {
/**
* struct nand_flash_dev - NAND Flash Device ID Structure
*
- * @name: Identify the device type
- * @id: device ID code
- * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
+ * @name: Identify the device type
+ * @id: device ID code
+ * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
* If the pagesize is 0, then the real pagesize
* and the eraseize are determined from the
* extended id bytes in the chip
- * @erasesize: Size of an erase block in the flash device.
- * @chipsize: Total chipsize in Mega Bytes
+ * @erasesize: Size of an erase block in the flash device.
+ * @chipsize: Total chipsize in Mega Bytes
* @options: Bitfield to store chip relevant options
*/
struct nand_flash_dev {
@@ -374,7 +374,7 @@ struct nand_flash_dev {
/**
* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
* @name: Manufacturer name
- * @id: manufacturer ID code of device.
+ * @id: manufacturer ID code of device.
*/
struct nand_manufacturers {
int id;
@@ -398,7 +398,7 @@ extern struct nand_manufacturers nand_manuf_ids[];
* blocks is reserved at the end of the device where the tables are
* written.
* @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
- * bad) block in the stored bbt
+ * bad) block in the stored bbt
* @pattern: pattern to identify bad block table or factory marked good /
* bad blocks, can be NULL, if len = 0
*
@@ -412,11 +412,11 @@ struct nand_bbt_descr {
int pages[NAND_MAX_CHIPS];
int offs;
int veroffs;
- uint8_t version[NAND_MAX_CHIPS];
+ uint8_t version[NAND_MAX_CHIPS];
int len;
- int maxblocks;
+ int maxblocks;
int reserved_block_code;
- uint8_t *pattern;
+ uint8_t *pattern;
};
/* Options for the bad block table descriptors */
@@ -428,7 +428,7 @@ struct nand_bbt_descr {
#define NAND_BBT_4BIT 0x00000004
#define NAND_BBT_8BIT 0x00000008
/* The bad block table is in the last good block of the device */
-#define NAND_BBT_LASTBLOCK 0x00000010
+#define NAND_BBT_LASTBLOCK 0x00000010
/* The bbt is at the given page, else we must scan for the bbt */
#define NAND_BBT_ABSPAGE 0x00000020
/* The bbt is at the given page, else we must scan for the bbt */
@@ -451,7 +451,7 @@ struct nand_bbt_descr {
#define NAND_BBT_SCAN2NDPAGE 0x00004000
/* The maximum number of blocks to scan for a bbt */
-#define NAND_BBT_SCAN_MAXBLOCKS 4
+#define NAND_BBT_SCAN_MAXBLOCKS 4
extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
diff --git a/include/ns16550.h b/include/ns16550.h
index 996d915..34888a1 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -7,7 +7,7 @@
* added prototypes for ns16550.c
* reduced no of com ports to 2
* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- *
+ *
* added support for port on 64-bit bus
* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
*/
diff --git a/include/pcmcia.h b/include/pcmcia.h
index 43d4510..8f564da 100644
--- a/include/pcmcia.h
+++ b/include/pcmcia.h
@@ -308,4 +308,14 @@ typedef struct {
#endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */
+#ifdef CONFIG_8xx
+extern u_int *pcmcia_pgcrx[];
+#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) \
+ || defined(CONFIG_PXA_PCMCIA)
+extern int check_ide_device(int slot);
+#endif
+
#endif /* _PCMCIA_H */
diff --git a/include/ppc440.h b/include/ppc440.h
index 53f14b5..d5a9f66 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -25,6 +25,8 @@
/*--------------------------------------------------------------------- */
/* Special Purpose Registers */
/*--------------------------------------------------------------------- */
+#define xer_reg 0x001
+#define lr_reg 0x008
#define dec 0x016 /* decrementer */
#define srr0 0x01a /* save/restore register 0 */
#define srr1 0x01b /* save/restore register 1 */
@@ -37,6 +39,8 @@
#define ivpr 0x03f /* interrupt prefix register */
#define usprg0 0x100 /* user special purpose register general 0 */
#define usprg1 0x110 /* user special purpose register general 1 */
+#define tblr 0x10c /* time base lower, read only */
+#define tbur 0x10d /* time base upper, read only */
#define sprg1 0x111 /* special purpose register general 1 */
#define sprg2 0x112 /* special purpose register general 2 */
#define sprg3 0x113 /* special purpose register general 3 */
@@ -78,7 +82,7 @@
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
@@ -167,12 +171,10 @@
#define sdr_malrbl 0x02a0
#define sdr_maltbs 0x02c0
#define sdr_malrbs 0x02e0
-#define sdr_pci0 0x0300
-#define sdr_usb0 0x0320
+#define sdr_pci0 0x0300
+#define sdr_usb0 0x0320
#define sdr_cust0 0x4000
-#define sdr_sdstp2 0x4001
#define sdr_cust1 0x4002
-#define sdr_sdstp3 0x4003
#define sdr_pfc0 0x4100 /* Pin Function 0 */
#define sdr_pfc1 0x4101 /* Pin Function 1 */
#define sdr_plbtr 0x4200
@@ -212,6 +214,551 @@
#define mem_dlycal 0x0084 /* delay line calibration register */
#define mem_eccesr 0x0098 /* ECC error status */
+#ifdef CONFIG_440GX
+#define sdr_amp 0x0240
+#define sdr_xpllc 0x01c1
+#define sdr_xplld 0x01c2
+#define sdr_xcr 0x01c0
+#define sdr_sdstp2 0x4001
+#define sdr_sdstp3 0x4003
+#endif /* CONFIG_440GX */
+
+#ifdef CONFIG_440SPE
+#undef sdr_sdstp2
+#define sdr_sdstp2 0x0022
+#undef sdr_sdstp3
+#define sdr_sdstp3 0x0023
+#define sdr_ddr0 0x00E1
+#define sdr_uart2 0x0122
+#define sdr_xcr0 0x01c0
+/* #define sdr_xcr1 0x01c3 only one PCIX - SG */
+/* #define sdr_xcr2 0x01c6 only one PCIX - SG */
+#define sdr_xpllc0 0x01c1
+#define sdr_xplld0 0x01c2
+#define sdr_xpllc1 0x01c4 /*notRCW - SG */
+#define sdr_xplld1 0x01c5 /*notRCW - SG */
+#define sdr_xpllc2 0x01c7 /*notRCW - SG */
+#define sdr_xplld2 0x01c8 /*notRCW - SG */
+#define sdr_amp0 0x0240
+#define sdr_amp1 0x0241
+#define sdr_cust2 0x4004
+#define sdr_cust3 0x4006
+#define sdr_sdstp4 0x4001
+#define sdr_sdstp5 0x4003
+#define sdr_sdstp6 0x4005
+#define sdr_sdstp7 0x4007
+
+/*----------------------------------------------------------------------------+
+| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
++----------------------------------------------------------------------------*/
+#define CCR0_PRE 0x40000000
+#define CCR0_CRPE 0x08000000
+#define CCR0_DSTG 0x00200000
+#define CCR0_DAPUIB 0x00100000
+#define CCR0_DTB 0x00008000
+#define CCR0_GICBT 0x00004000
+#define CCR0_GDCBT 0x00002000
+#define CCR0_FLSTA 0x00000100
+#define CCR0_ICSLC_MASK 0x0000000C
+#define CCR0_ICSLT_MASK 0x00000003
+#define CCR1_TCS_MASK 0x00000080
+#define CCR1_TCS_INTCLK 0x00000000
+#define CCR1_TCS_EXTCLK 0x00000080
+#define MMUCR_SEOA 0x01000000
+#define MMUCR_U1TE 0x00400000
+#define MMUCR_U2SWOAE 0x00200000
+#define MMUCR_DULXE 0x00800000
+#define MMUCR_IULXE 0x00400000
+#define MMUCR_STS 0x00100000
+#define MMUCR_STID_MASK 0x000000FF
+
+#define SDR0_CFGADDR 0x00E
+#define SDR0_CFGDATA 0x00F
+
+/******************************************************************************
+ * PCI express defines
+ ******************************************************************************/
+#define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */
+#define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */
+#define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */
+#define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */
+#define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */
+#define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */
+#define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */
+#define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */
+#define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */
+#define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */
+#define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */
+#define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */
+#define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */
+#define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */
+#define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */
+#define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */
+#define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */
+#define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */
+#define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */
+#define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */
+#define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */
+#define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */
+#define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */
+#define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */
+#define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */
+#define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */
+#define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */
+#define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */
+#define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */
+#define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */
+#define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */
+#define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */
+#define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */
+
+#define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */
+#define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */
+#define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */
+#define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */
+#define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */
+#define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */
+#define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */
+#define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */
+#define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */
+#define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */
+#define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */
+#define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */
+#define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */
+#define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */
+#define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */
+#define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */
+#define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */
+#define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */
+#define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */
+#define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */
+#define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */
+#define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */
+#define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */
+#define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */
+#define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */
+#define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */
+#define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */
+#define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */
+#define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */
+#define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */
+#define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */
+#define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */
+#define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */
+#define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */
+#define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */
+#define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */
+#define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */
+#define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */
+#define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */
+#define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */
+#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
+#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
+#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
+
+/*----------------------------------------------------------------------------+
+| SDRAM Controller
++----------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------+
+| SDRAM DLYCAL Options
++-----------------------------------------------------------------------------*/
+#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
+#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
+#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
+
+/*----------------------------------------------------------------------------+
+| Memory queue defines
++----------------------------------------------------------------------------*/
+/* A REVOIR versus RWC - SG*/
+#define SDRAMQ_DCR_BASE 0x040
+
+#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
+#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
+#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
+#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
+#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
+#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
+#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
+#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
+#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
+#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
+#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
+#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
+#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
+#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
+#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
+
+/*-----------------------------------------------------------------------------+
+| Memory Bank 0-7 configuration
++-----------------------------------------------------------------------------*/
+#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
+#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
+#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
+#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
+#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
+#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
+#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
+#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
+#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
+#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
+#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
+#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
+#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
+#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
+#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
+#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
+#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
+
+/*----------------------------------------------------------------------------+
+| Memory controller defines
++----------------------------------------------------------------------------*/
+#define SDRAMC_DCR_BASE 0x010
+#define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */
+#define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */
+
+/* A REVOIR versus specs 4 bank - SG*/
+#define SDRAM_MCSTAT 0x14 /* memory controller status */
+#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
+#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
+#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
+#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
+#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
+#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
+#define SDRAM_CODT 0x26 /* on die termination for controller */
+#define SDRAM_VVPR 0x27 /* variable VRef programmming */
+#define SDRAM_OPARS 0x28 /* on chip driver control setup */
+#define SDRAM_OPART 0x29 /* on chip driver control trigger */
+#define SDRAM_RTR 0x30 /* refresh timer */
+#define SDRAM_PMIT 0x34 /* power management idle timer */
+#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
+#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
+#define SDRAM_MB2CF 0x48
+#define SDRAM_MB3CF 0x4C
+#define SDRAM_INITPLR0 0x50 /* manual initialization control */
+#define SDRAM_INITPLR1 0x51 /* manual initialization control */
+#define SDRAM_INITPLR2 0x52 /* manual initialization control */
+#define SDRAM_INITPLR3 0x53 /* manual initialization control */
+#define SDRAM_INITPLR4 0x54 /* manual initialization control */
+#define SDRAM_INITPLR5 0x55 /* manual initialization control */
+#define SDRAM_INITPLR6 0x56 /* manual initialization control */
+#define SDRAM_INITPLR7 0x57 /* manual initialization control */
+#define SDRAM_INITPLR8 0x58 /* manual initialization control */
+#define SDRAM_INITPLR9 0x59 /* manual initialization control */
+#define SDRAM_INITPLR10 0x5a /* manual initialization control */
+#define SDRAM_INITPLR11 0x5b /* manual initialization control */
+#define SDRAM_INITPLR12 0x5c /* manual initialization control */
+#define SDRAM_INITPLR13 0x5d /* manual initialization control */
+#define SDRAM_INITPLR14 0x5e /* manual initialization control */
+#define SDRAM_INITPLR15 0x5f /* manual initialization control */
+#define SDRAM_RQDC 0x70 /* read DQS delay control */
+#define SDRAM_RFDC 0x74 /* read feedback delay control */
+#define SDRAM_RDCC 0x78 /* read data capture control */
+#define SDRAM_DLCR 0x7A /* delay line calibration */
+#define SDRAM_CLKTR 0x80 /* DDR clock timing */
+#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
+#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
+#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
+#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
+#define SDRAM_MMODE 0x88 /* memory mode */
+#define SDRAM_MEMODE 0x89 /* memory extended mode */
+#define SDRAM_ECCCR 0x98 /* ECC error status */
+#define SDRAM_CID 0xA4 /* core ID */
+#define SDRAM_RID 0xA8 /* revision ID */
+
+/*-----------------------------------------------------------------------------+
+| Memory Controller Status
++-----------------------------------------------------------------------------*/
+#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
+#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
+#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
+#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
+#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
+#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
+
+/*-----------------------------------------------------------------------------+
+| Memory Controller Options 1
++-----------------------------------------------------------------------------*/
+#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
+#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
+#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
+#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
+#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
+#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
+#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
+#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
+#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
+#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
+#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
+#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
+#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
+#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
+#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
+#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
+#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
+#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
+#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
+#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
+#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
+#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
+#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
+#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
+#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
+#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
+#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
+#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
+#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
+#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
+#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
+#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
+#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
+#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
+#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
+
+/*-----------------------------------------------------------------------------+
+| Memory Controller Options 2
++-----------------------------------------------------------------------------*/
+#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
+#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
+#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
+#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
+#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
+#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
+#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
+#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
+#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
+#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
+#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
+#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
+#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
+#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
+#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
+#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
+#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
+#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Refresh Timer Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RTR_RINT_MASK 0xFFF80000
+#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
+#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Read DQS Delay Control Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RQDC_RQDE_MASK 0x80000000
+#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
+#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
+#define SDRAM_RQDC_RQFD_MASK 0x000001FF
+#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
+
+#define SDRAM_RQDC_RQFD_MAX 0x1FF
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Read Data Capture Control Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RDCC_RDSS_MASK 0xC0000000
+#define SDRAM_RDCC_RDSS_T1 0x00000000
+#define SDRAM_RDCC_RDSS_T2 0x40000000
+#define SDRAM_RDCC_RDSS_T3 0x80000000
+#define SDRAM_RDCC_RDSS_T4 0xC0000000
+#define SDRAM_RDCC_RSAE_MASK 0x00000001
+#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
+#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Read Feedback Delay Control Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_RFDC_ARSE_MASK 0x80000000
+#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
+#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
+#define SDRAM_RFDC_RFOS_MASK 0x007F0000
+#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define SDRAM_RFDC_RFFD_MASK 0x000003FF
+#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+
+#define SDRAM_RFDC_RFFD_MAX 0x7FF
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Delay Line Calibration Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_DLCR_DCLM_MASK 0x80000000
+#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
+#define SDRAM_DLCR_DCLM_AUTO 0x00000000
+#define SDRAM_DLCR_DLCR_MASK 0x08000000
+#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
+#define SDRAM_DLCR_DLCR_IDLE 0x00000000
+#define SDRAM_DLCR_DLCS_MASK 0x07000000
+#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
+#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
+#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
+#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
+#define SDRAM_DLCR_DLCS_ERROR 0x04000000
+#define SDRAM_DLCR_DLCV_MASK 0x000001FF
+#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
+#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Controller On Die Termination Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_CODT_ODT_ON 0x80000000
+#define SDRAM_CODT_ODT_OFF 0x00000000
+#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
+#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
+#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
+#define SDRAM_CODT_DQS_MASK 0x00000010
+#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
+#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
+#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
+#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
+#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
+#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
+#define SDRAM_CODT_IO_HIZ 0x00000000
+#define SDRAM_CODT_IO_NMODE 0x00000001
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Mode Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_MMODE_WR_MASK 0x00000E00
+#define SDRAM_MMODE_WR_DDR1 0x00000000
+#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
+#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
+#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
+#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
+#define SDRAM_MMODE_DCL_MASK 0x00000070
+#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
+#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
+#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
+#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
+#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
+#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
+#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
+#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
+#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Extended Mode Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_MEMODE_DIC_MASK 0x00000002
+#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
+#define SDRAM_MEMODE_DIC_WEAK 0x00000002
+#define SDRAM_MEMODE_DLL_MASK 0x00000001
+#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
+#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
+#define SDRAM_MEMODE_RTT_MASK 0x00000044
+#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
+#define SDRAM_MEMODE_RTT_75OHM 0x00000004
+#define SDRAM_MEMODE_RTT_150OHM 0x00000040
+#define SDRAM_MEMODE_DQS_MASK 0x00000400
+#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
+#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Clock Timing Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
+#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
+#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
+
+/*-----------------------------------------------------------------------------+
+| SDRAM Write Timing Register
++-----------------------------------------------------------------------------*/
+#define SDRAM_WRDTR_LLWP_MASK 0x10000000
+#define SDRAM_WRDTR_LLWP_DIS 0x10000000
+#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
+#define SDRAM_WRDTR_WTR_MASK 0x0E000000
+#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
+#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
+#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
+
+/*-----------------------------------------------------------------------------+
+| SDRAM SDTR1 Options
++-----------------------------------------------------------------------------*/
+#define SDRAM_SDTR1_LDOF_MASK 0x80000000
+#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
+#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
+#define SDRAM_SDTR1_RTW_MASK 0x00F00000
+#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
+#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
+#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
+#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
+#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
+#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
+#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
+#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
+
+/*-----------------------------------------------------------------------------+
+| SDRAM SDTR2 Options
++-----------------------------------------------------------------------------*/
+#define SDRAM_SDTR2_RCD_MASK 0xF0000000
+#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
+#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
+#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
+#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
+#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
+#define SDRAM_SDTR2_WTR_MASK 0x0F000000
+#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
+#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
+#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
+#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
+#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
+#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
+#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
+#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
+#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
+#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
+#define SDRAM_SDTR2_WPC_MASK 0x0000F000
+#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
+#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
+#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
+#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
+#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
+#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
+#define SDRAM_SDTR2_RPC_MASK 0x00000F00
+#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
+#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
+#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
+#define SDRAM_SDTR2_RP_MASK 0x000000F0
+#define SDRAM_SDTR2_RP_3_CLK 0x00000030
+#define SDRAM_SDTR2_RP_4_CLK 0x00000040
+#define SDRAM_SDTR2_RP_5_CLK 0x00000050
+#define SDRAM_SDTR2_RP_6_CLK 0x00000060
+#define SDRAM_SDTR2_RP_7_CLK 0x00000070
+#define SDRAM_SDTR2_RRD_MASK 0x0000000F
+#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
+#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
+
+/*-----------------------------------------------------------------------------+
+| SDRAM SDTR3 Options
++-----------------------------------------------------------------------------*/
+#define SDRAM_SDTR3_RAS_MASK 0x1F000000
+#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define SDRAM_SDTR3_RC_MASK 0x001F0000
+#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
+#define SDRAM_SDTR3_XCS_MASK 0x00001F00
+#define SDRAM_SDTR3_XCS 0x00000D00
+#define SDRAM_SDTR3_RFC_MASK 0x0000003F
+#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
+
+/*-----------------------------------------------------------------------------+
+| Memory Bank 0-1 configuration
++-----------------------------------------------------------------------------*/
+#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
+#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
+#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
+#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
+#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
+#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
+#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
+#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
+#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
+#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
+#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
+#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
+#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
+#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
+#endif /* CONFIG_440SPE */
+
/*-----------------------------------------------------------------------------
| External Bus Controller
+----------------------------------------------------------------------------*/
@@ -503,7 +1050,7 @@
/*-----------------------------------------------------------------------------
| L2 Cache
+----------------------------------------------------------------------------*/
-#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define L2_CACHE_BASE 0x030
#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
@@ -526,7 +1073,7 @@
| Clocking, Power Management and Chip Control
+----------------------------------------------------------------------------*/
#define CNTRL_DCR_BASE 0x0b0
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
@@ -574,6 +1121,30 @@
#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
+#if defined(CONFIG_440SPE)
+#define UIC2_DCR_BASE 0xe0
+#define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */
+#define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */
+#define uic2er (UIC0_DCR_BASE+0x2) /* UIC2 enable */
+#define uic2cr (UIC0_DCR_BASE+0x3) /* UIC2 critical */
+#define uic2pr (UIC0_DCR_BASE+0x4) /* UIC2 polarity */
+#define uic2tr (UIC0_DCR_BASE+0x5) /* UIC2 triggering */
+#define uic2msr (UIC0_DCR_BASE+0x6) /* UIC2 masked status */
+#define uic2vr (UIC0_DCR_BASE+0x7) /* UIC2 vector */
+#define uic2vcr (UIC0_DCR_BASE+0x8) /* UIC2 vector configuration */
+
+#define UIC3_DCR_BASE 0xf0
+#define uic3sr (UIC1_DCR_BASE+0x0) /* UIC3 status-Read Clear */
+#define uic3srs (UIC0_DCR_BASE+0x1) /* UIC3 status-Read Set */
+#define uic3er (UIC1_DCR_BASE+0x2) /* UIC3 enable */
+#define uic3cr (UIC1_DCR_BASE+0x3) /* UIC3 critical */
+#define uic3pr (UIC1_DCR_BASE+0x4) /* UIC3 polarity */
+#define uic3tr (UIC1_DCR_BASE+0x5) /* UIC3 triggering */
+#define uic3msr (UIC1_DCR_BASE+0x6) /* UIC3 masked status */
+#define uic3vr (UIC1_DCR_BASE+0x7) /* UIC3 vector */
+#define uic3vcr (UIC1_DCR_BASE+0x8) /* UIC3 vector configuration */
+#endif /* CONFIG_440SPE */
+
#if defined(CONFIG_440GX)
#define UIC2_DCR_BASE 0x210
#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
@@ -607,6 +1178,103 @@
#define uicvr uic0vr
#define uicvcr uic0vcr
+#if defined(CONFIG_440SPE)
+/*----------------------------------------------------------------------------+
+| Clock / Power-on-reset DCR's.
++----------------------------------------------------------------------------*/
+#define CPR0_CFGADDR 0x00C
+#define CPR0_CFGDATA 0x00D
+
+#define CPR0_CLKUPD 0x20
+#define CPR0_CLKUPD_BSY_MASK 0x80000000
+#define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
+#define CPR0_CLKUPD_BSY_BUSY 0x80000000
+#define CPR0_CLKUPD_CUI_MASK 0x80000000
+#define CPR0_CLKUPD_CUI_DISABLE 0x00000000
+#define CPR0_CLKUPD_CUI_ENABLE 0x80000000
+#define CPR0_CLKUPD_CUD_MASK 0x40000000
+#define CPR0_CLKUPD_CUD_DISABLE 0x00000000
+#define CPR0_CLKUPD_CUD_ENABLE 0x40000000
+
+#define CPR0_PLLC 0x40
+#define CPR0_PLLC_RST_MASK 0x80000000
+#define CPR0_PLLC_RST_PLLLOCKED 0x00000000
+#define CPR0_PLLC_RST_PLLRESET 0x80000000
+#define CPR0_PLLC_ENG_MASK 0x40000000
+#define CPR0_PLLC_ENG_DISABLE 0x00000000
+#define CPR0_PLLC_ENG_ENABLE 0x40000000
+#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
+#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
+#define CPR0_PLLC_SRC_MASK 0x20000000
+#define CPR0_PLLC_SRC_PLLOUTA 0x00000000
+#define CPR0_PLLC_SRC_PLLOUTB 0x20000000
+#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
+#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
+#define CPR0_PLLC_SEL_MASK 0x07000000
+#define CPR0_PLLC_SEL_PLLOUT 0x00000000
+#define CPR0_PLLC_SEL_CPU 0x01000000
+#define CPR0_PLLC_SEL_EBC 0x05000000
+#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
+#define CPR0_PLLC_TUNE_MASK 0x000003FF
+#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+
+#define CPR0_PLLD 0x60
+#define CPR0_PLLD_FBDV_MASK 0x1F000000
+#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
+#define CPR0_PLLD_FWDVA_MASK 0x000F0000
+#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
+#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
+#define CPR0_PLLD_FWDVB_MASK 0x00000700
+#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
+#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
+#define CPR0_PLLD_LFBDV_MASK 0x0000003F
+#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
+#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
+
+#define CPR0_PRIMAD 0x80
+#define CPR0_PRIMAD_PRADV0_MASK 0x07000000
+#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+
+#define CPR0_PRIMBD 0xA0
+#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
+#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+
+#define CPR0_OPBD 0xC0
+#define CPR0_OPBD_OPBDV0_MASK 0x03000000
+#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+
+#define CPR0_PERD 0xE0
+#define CPR0_PERD_PERDV0_MASK 0x03000000
+#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+
+#define CPR0_MALD 0x100
+#define CPR0_MALD_MALDV0_MASK 0x03000000
+#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+
+#define CPR0_ICFG 0x140
+#define CPR0_ICFG_RLI_MASK 0x80000000
+#define CPR0_ICFG_RLI_RESETCPR 0x00000000
+#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
+#define CPR0_ICFG_ICS_MASK 0x00000007
+#define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
+#define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
+
+/************************/
+/* IIC defines */
+/************************/
+#define IIC0_MMIO_BASE 0xA0000400
+#define IIC1_MMIO_BASE 0xA0000500
+
+#endif /* CONFIG_440SP */
+
/*-----------------------------------------------------------------------------
| DMA
+----------------------------------------------------------------------------*/
@@ -722,7 +1390,7 @@
#define UIC_GPTCT 0x00000004 /* GPT count timer */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
-#else /* CONFIG_440SP */
+#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
@@ -755,7 +1423,40 @@
#define UIC_EIR6 0x00000004 /* External interrupt 6 */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
-#endif /* CONFIG_440SP */
+#elif !defined(CONFIG_440SPE)
+#define UIC_U0 0x80000000 /* UART 0 */
+#define UIC_U1 0x40000000 /* UART 1 */
+#define UIC_IIC0 0x20000000 /* IIC */
+#define UIC_IIC1 0x10000000 /* IIC */
+#define UIC_PIM 0x08000000 /* PCI inbound message */
+#define UIC_PCRW 0x04000000 /* PCI command register write */
+#define UIC_PPM 0x02000000 /* PCI power management */
+#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
+#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
+#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
+#define UIC_MTE 0x00200000 /* MAL TXEOB */
+#define UIC_MRE 0x00100000 /* MAL RXEOB */
+#define UIC_D0 0x00080000 /* DMA channel 0 */
+#define UIC_D1 0x00040000 /* DMA channel 1 */
+#define UIC_D2 0x00020000 /* DMA channel 2 */
+#define UIC_D3 0x00010000 /* DMA channel 3 */
+#define UIC_RSVD0 0x00008000 /* Reserved */
+#define UIC_RSVD1 0x00004000 /* Reserved */
+#define UIC_CT0 0x00002000 /* GPT compare timer 0 */
+#define UIC_CT1 0x00001000 /* GPT compare timer 1 */
+#define UIC_CT2 0x00000800 /* GPT compare timer 2 */
+#define UIC_CT3 0x00000400 /* GPT compare timer 3 */
+#define UIC_CT4 0x00000200 /* GPT compare timer 4 */
+#define UIC_EIR0 0x00000100 /* External interrupt 0 */
+#define UIC_EIR1 0x00000080 /* External interrupt 1 */
+#define UIC_EIR2 0x00000040 /* External interrupt 2 */
+#define UIC_EIR3 0x00000020 /* External interrupt 3 */
+#define UIC_EIR4 0x00000010 /* External interrupt 4 */
+#define UIC_EIR5 0x00000008 /* External interrupt 5 */
+#define UIC_EIR6 0x00000004 /* External interrupt 6 */
+#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
+#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
+#endif /* CONFIG_440GX */
/* For compatibility with 405 code */
#define UIC_MAL_TXEOB UIC_MTE
@@ -797,7 +1498,40 @@
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* Reserved */
#define UIC_XOR 0x00000001 /* XOR */
-#else /* CONFIG_440SP */
+#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
+#define UIC_MS 0x80000000 /* MAL SERR */
+#define UIC_MTDE 0x40000000 /* MAL TXDE */
+#define UIC_MRDE 0x20000000 /* MAL RXDE */
+#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
+#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
+#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
+#define UIC_EBMI 0x02000000 /* EBMI interrupt status */
+#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
+#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
+#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
+#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
+#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
+#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
+#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
+#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
+#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
+#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
+#define UIC_PPMI 0x00004000 /* PPM interrupt status */
+#define UIC_EIR7 0x00002000 /* External interrupt 7 */
+#define UIC_EIR8 0x00001000 /* External interrupt 8 */
+#define UIC_EIR9 0x00000800 /* External interrupt 9 */
+#define UIC_EIR10 0x00000400 /* External interrupt 10 */
+#define UIC_EIR11 0x00000200 /* External interrupt 11 */
+#define UIC_EIR12 0x00000100 /* External interrupt 12 */
+#define UIC_SRE 0x00000080 /* Serial ROM error */
+#define UIC_RSVD2 0x00000040 /* Reserved */
+#define UIC_RSVD3 0x00000020 /* Reserved */
+#define UIC_PAE 0x00000010 /* PCI asynchronous error */
+#define UIC_ETH0 0x00000008 /* Ethernet 0 */
+#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
+#define UIC_ETH1 0x00000002 /* Ethernet 1 */
+#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
+#elif !defined(CONFIG_440SPE)
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_MRDE 0x20000000 /* MAL RXDE */
@@ -890,6 +1624,117 @@
#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
#endif /* CONFIG_440GX */
+/*---------------------------------------------------------------------------+
+| Universal interrupt controller interrupts
++---------------------------------------------------------------------------*/
+#if defined(CONFIG_440SPE)
+/*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */
+/*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */
+#define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */
+#define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */
+#define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */
+#define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */
+#define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */
+#define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */
+
+#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
+ UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
+/*---------------------------------------------------------------------------+
+| Universal interrupt controller 0 interrupts (UIC0)
++---------------------------------------------------------------------------*/
+#define UIC_U0 0x80000000 /* UART 0 */
+#define UIC_U1 0x40000000 /* UART 1 */
+#define UIC_IIC0 0x20000000 /* IIC */
+#define UIC_IIC1 0x10000000 /* IIC */
+#define UIC_PIM 0x08000000 /* PCI inbound message */
+#define UIC_PCRW 0x04000000 /* PCI command register write */
+#define UIC_PPM 0x02000000 /* PCI power management */
+#define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */
+#define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */
+#define UIC_EIR15 0x00400000 /* External intp 15 */
+#define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */
+#define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */
+#define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */
+#define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */
+#define UIC_EIR14 0x00002000 /* External interrupt 14 */
+#define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */
+#define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */
+#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
+#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
+#define UIC_I2OID 0x00000100 /* I2O inbound door bell */
+#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
+#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
+#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
+#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
+#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
+#define UIC_CPTCNT 0x00000004 /* GPT Count Timer */
+/*---------------------------------------------------------------------------+
+| Universal interrupt controller 1 interrupts (UIC1)
++---------------------------------------------------------------------------*/
+#define UIC_EIR13 0x80000000 /* externei intp 13 */
+#define UIC_MS 0x40000000 /* MAL SERR */
+#define UIC_MTDE 0x20000000 /* MAL TXDE */
+#define UIC_MRDE 0x10000000 /* MAL RXDE */
+#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
+#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
+#define UIC_MTE 0x02000000 /* MAL TXEOB */
+#define UIC_MRE 0x01000000 /* MAL RXEOB */
+#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
+#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
+#define UIC_MSI3 0x00200000 /* PCI MSI level 3 */
+#define UIC_L2C 0x00100000 /* L2 cache */
+#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
+#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
+#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
+#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
+#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
+#define UIC_EIR12 0x00004000 /* External interrupt 12 */
+#define UIC_EIR11 0x00002000 /* External interrupt 11 */
+#define UIC_EIR10 0x00001000 /* External interrupt 10 */
+#define UIC_EIR9 0x00000800 /* External interrupt 9 */
+#define UIC_EIR8 0x00000400 /* External interrupt 8 */
+#define UIC_DMAE 0x00000200 /* dma error */
+#define UIC_I2OE 0x00000100 /* i2o error */
+#define UIC_SRE 0x00000080 /* Serial ROM error */
+#define UIC_PCIXAE 0x00000040 /* Pcix0 async error */
+#define UIC_EIR7 0x00000020 /* External interrupt 7 */
+#define UIC_EIR6 0x00000010 /* External interrupt 6 */
+#define UIC_ETH0 0x00000008 /* Ethernet 0 */
+#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
+#define UIC_ETH1 0x00000002 /* reserved */
+#define UIC_XOR 0x00000001 /* xor */
+
+/*---------------------------------------------------------------------------+
+| Universal interrupt controller 2 interrupts (UIC2)
++---------------------------------------------------------------------------*/
+#define UIC_PEOAL 0x80000000 /* PE0 AL */
+#define UIC_PEOVA 0x40000000 /* PE0 VPD access */
+#define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */
+#define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */
+#define UIC_PE0TCR 0x08000000 /* PE0 TCR */
+#define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */
+#define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */
+#define UIC_PE1AL 0x00800000 /* PE1 AL */
+#define UIC_PE1VA 0x00400000 /* PE1 VPD access */
+#define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */
+#define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */
+#define UIC_PE1TCR 0x00080000 /* PE1 TCR */
+#define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */
+#define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */
+#define UIC_PE2AL 0x00008000 /* PE2 AL */
+#define UIC_PE2VA 0x00004000 /* PE2 VPD access */
+#define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */
+#define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */
+#define UIC_PE2TCR 0x00000800 /* PE2 TCR */
+#define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */
+#define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */
+#define UIC_EIR5 0x00000080 /* External interrupt 5 */
+#define UIC_EIR4 0x00000040 /* External interrupt 4 */
+#define UIC_EIR3 0x00000020 /* External interrupt 3 */
+#define UIC_EIR2 0x00000010 /* External interrupt 2 */
+#define UIC_EIR1 0x00000008 /* External interrupt 1 */
+#define UIC_EIR0 0x00000004 /* External interrupt 0 */
+#endif /* CONFIG_440SPE */
/*-----------------------------------------------------------------------------+
| External Bus Controller Bit Settings
@@ -981,6 +1826,432 @@
/*-----------------------------------------------------------------------------+
| SDR0 Bit Settings
+-----------------------------------------------------------------------------*/
+#if defined(CONFIG_440SPE)
+#define SDR0_CP440 0x0180
+#define SDR0_CP440_ERPN_MASK 0x30000000
+#define SDR0_CP440_ERPN_MASK_HI 0x3000
+#define SDR0_CP440_ERPN_MASK_LO 0x0000
+#define SDR0_CP440_ERPN_EBC 0x10000000
+#define SDR0_CP440_ERPN_EBC_HI 0x1000
+#define SDR0_CP440_ERPN_EBC_LO 0x0000
+#define SDR0_CP440_ERPN_PCI 0x20000000
+#define SDR0_CP440_ERPN_PCI_HI 0x2000
+#define SDR0_CP440_ERPN_PCI_LO 0x0000
+#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
+#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
+#define SDR0_CP440_NTO1_MASK 0x00000002
+#define SDR0_CP440_NTO1_NTOP 0x00000000
+#define SDR0_CP440_NTO1_NTO1 0x00000002
+#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
+#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
+#define SDR0_CFGADDR 0x00E /*already defined line 277 */
+#define SDR0_CFGDATA 0x00F
+
+
+#define SDR0_SDSTP0 0x0020
+#define SDR0_SDSTP0_ENG_MASK 0x80000000
+#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
+#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
+#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
+#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
+#define SDR0_SDSTP0_SRC_MASK 0x40000000
+#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
+#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
+#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
+#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
+#define SDR0_SDSTP0_SEL_MASK 0x38000000
+#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
+#define SDR0_SDSTP0_SEL_CPU 0x08000000
+#define SDR0_SDSTP0_SEL_EBC 0x28000000
+#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
+#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
+#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
+#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
+#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
+#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
+#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
+#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
+#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
+#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
+#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
+#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
+#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
+#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
+#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
+#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
+#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
+#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
+#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
+#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
+
+
+#define SDR0_SDSTP1 0x0021
+#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
+#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
+#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
+#define SDR0_SDSTP1_PERDV0_MASK 0x03000000
+#define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+#define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
+#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
+#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
+#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
+#define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
+#define SDR0_SDSTP1_DDR1_MODE 0x00100000
+#define SDR0_SDSTP1_DDR2_MODE 0x00200000
+#define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
+#define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
+#define SDR0_SDSTP1_ERPN_MASK 0x00080000
+#define SDR0_SDSTP1_ERPN_EBC 0x00000000
+#define SDR0_SDSTP1_ERPN_PCI 0x00080000
+#define SDR0_SDSTP1_PAE_MASK 0x00040000
+#define SDR0_SDSTP1_PAE_DISABLE 0x00000000
+#define SDR0_SDSTP1_PAE_ENABLE 0x00040000
+#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
+#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
+#define SDR0_SDSTP1_PHCE_MASK 0x00020000
+#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
+#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
+#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
+#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
+#define SDR0_SDSTP1_PISE_MASK 0x00010000
+#define SDR0_SDSTP1_PISE_DISABLE 0x00000000
+#define SDR0_SDSTP1_PISE_ENABLE 0x00001000
+#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
+#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
+#define SDR0_SDSTP1_PCWE_MASK 0x00008000
+#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
+#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
+#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
+#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
+#define SDR0_SDSTP1_PPIM_MASK 0x00007800
+#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
+#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
+#define SDR0_SDSTP1_PR64E_MASK 0x00000400
+#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
+#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
+#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
+#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
+#define SDR0_SDSTP1_PXFS_MASK 0x00000300
+#define SDR0_SDSTP1_PXFS_100_133 0x00000000
+#define SDR0_SDSTP1_PXFS_66_100 0x00000100
+#define SDR0_SDSTP1_PXFS_50_66 0x00000200
+#define SDR0_SDSTP1_PXFS_0_50 0x00000300
+#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
+#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
+#define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
+#define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
+#define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
+#define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
+#define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
+#define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
+#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
+#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
+#define SDR0_SDSTP1_ETH_MASK 0x00000004
+#define SDR0_SDSTP1_ETH_10_100 0x00000000
+#define SDR0_SDSTP1_ETH_GIGA 0x00000004
+#define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
+#define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
+#define SDR0_SDSTP1_NTO1_MASK 0x00000001
+#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
+#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
+#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
+#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
+
+#define SDR0_SDSTP2 0x0022
+#define SDR0_SDSTP2_P1AE_MASK 0x80000000
+#define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
+#define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
+#define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
+#define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
+#define SDR0_SDSTP2_P1HCE_MASK 0x40000000
+#define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
+#define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
+#define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
+#define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
+#define SDR0_SDSTP2_P1ISE_MASK 0x20000000
+#define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
+#define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
+#define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
+#define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
+#define SDR0_SDSTP2_P1CWE_MASK 0x10000000
+#define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
+#define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
+#define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
+#define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
+#define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
+#define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
+#define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
+#define SDR0_SDSTP2_P1R64E_MASK 0x00800000
+#define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
+#define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
+#define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
+#define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
+#define SDR0_SDSTP2_P1XFS_MASK 0x00600000
+#define SDR0_SDSTP2_P1XFS_100_133 0x00000000
+#define SDR0_SDSTP2_P1XFS_66_100 0x00200000
+#define SDR0_SDSTP2_P1XFS_50_66 0x00400000
+#define SDR0_SDSTP2_P1XFS_0_50 0x00600000
+#define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
+#define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
+#define SDR0_SDSTP2_P2AE_MASK 0x00040000
+#define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
+#define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
+#define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
+#define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
+#define SDR0_SDSTP2_P2HCE_MASK 0x00020000
+#define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
+#define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
+#define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
+#define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
+#define SDR0_SDSTP2_P2ISE_MASK 0x00010000
+#define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
+#define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
+#define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
+#define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
+#define SDR0_SDSTP2_P2CWE_MASK 0x00008000
+#define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
+#define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
+#define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
+#define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
+#define SDR0_SDSTP2_P2PIM_MASK 0x00007800
+#define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
+#define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
+#define SDR0_SDSTP2_P2XFS_MASK 0x00000300
+#define SDR0_SDSTP2_P2XFS_100_133 0x00000000
+#define SDR0_SDSTP2_P2XFS_66_100 0x00000100
+#define SDR0_SDSTP2_P2XFS_50_66 0x00000200
+#define SDR0_SDSTP2_P2XFS_0_50 0x00000100
+#define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
+#define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
+
+#define SDR0_SDSTP3 0x0023
+
+#define SDR0_PINSTP 0x0040
+#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
+#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
+#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
+#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
+#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
+#define SDR0_SDCS 0x0060
+#define SDR0_ECID0 0x0080
+#define SDR0_ECID1 0x0081
+#define SDR0_ECID2 0x0082
+#define SDR0_JTAG 0x00C0
+
+#define SDR0_DDR0 0x00E1
+#define SDR0_DDR0_DPLLRST 0x80000000
+#define SDR0_DDR0_DDRM_MASK 0x60000000
+#define SDR0_DDR0_DDRM_DDR1 0x20000000
+#define SDR0_DDR0_DDRM_DDR2 0x40000000
+#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
+#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
+#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
+#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
+
+#define SDR0_UART0 0x0120
+#define SDR0_UART1 0x0121
+#define SDR0_UART2 0x0122
+#define SDR0_UARTX_UXICS_MASK 0xF0000000
+#define SDR0_UARTX_UXICS_PLB 0x20000000
+#define SDR0_UARTX_UXEC_MASK 0x00800000
+#define SDR0_UARTX_UXEC_INT 0x00000000
+#define SDR0_UARTX_UXEC_EXT 0x00800000
+#define SDR0_UARTX_UXDIV_MASK 0x000000FF
+#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
+#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
+
+#define SDR0_CP440 0x0180
+#define SDR0_CP440_ERPN_MASK 0x30000000
+#define SDR0_CP440_ERPN_MASK_HI 0x3000
+#define SDR0_CP440_ERPN_MASK_LO 0x0000
+#define SDR0_CP440_ERPN_EBC 0x10000000
+#define SDR0_CP440_ERPN_EBC_HI 0x1000
+#define SDR0_CP440_ERPN_EBC_LO 0x0000
+#define SDR0_CP440_ERPN_PCI 0x20000000
+#define SDR0_CP440_ERPN_PCI_HI 0x2000
+#define SDR0_CP440_ERPN_PCI_LO 0x0000
+#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
+#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
+#define SDR0_CP440_NTO1_MASK 0x00000002
+#define SDR0_CP440_NTO1_NTOP 0x00000000
+#define SDR0_CP440_NTO1_NTO1 0x00000002
+#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
+#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
+
+#define SDR0_XCR0 0x01C0
+#define SDR0_XCR1 0x01C3
+#define SDR0_XCR2 0x01C6
+#define SDR0_XCRn_PAE_MASK 0x80000000
+#define SDR0_XCRn_PAE_DISABLE 0x00000000
+#define SDR0_XCRn_PAE_ENABLE 0x80000000
+#define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
+#define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
+#define SDR0_XCRn_PHCE_MASK 0x40000000
+#define SDR0_XCRn_PHCE_DISABLE 0x00000000
+#define SDR0_XCRn_PHCE_ENABLE 0x40000000
+#define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
+#define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
+#define SDR0_XCRn_PISE_MASK 0x20000000
+#define SDR0_XCRn_PISE_DISABLE 0x00000000
+#define SDR0_XCRn_PISE_ENABLE 0x20000000
+#define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
+#define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
+#define SDR0_XCRn_PCWE_MASK 0x10000000
+#define SDR0_XCRn_PCWE_DISABLE 0x00000000
+#define SDR0_XCRn_PCWE_ENABLE 0x10000000
+#define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
+#define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
+#define SDR0_XCRn_PPIM_MASK 0x0F000000
+#define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
+#define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
+#define SDR0_XCRn_PR64E_MASK 0x00800000
+#define SDR0_XCRn_PR64E_DISABLE 0x00000000
+#define SDR0_XCRn_PR64E_ENABLE 0x00800000
+#define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
+#define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
+#define SDR0_XCRn_PXFS_MASK 0x00600000
+#define SDR0_XCRn_PXFS_100_133 0x00000000
+#define SDR0_XCRn_PXFS_66_100 0x00200000
+#define SDR0_XCRn_PXFS_50_66 0x00400000
+#define SDR0_XCRn_PXFS_0_33 0x00600000
+#define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
+#define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
+
+#define SDR0_XPLLC0 0x01C1
+#define SDR0_XPLLD0 0x01C2
+#define SDR0_XPLLC1 0x01C4
+#define SDR0_XPLLD1 0x01C5
+#define SDR0_XPLLC2 0x01C7
+#define SDR0_XPLLD2 0x01C8
+#define SDR0_SRST 0x0200
+#define SDR0_SLPIPE 0x0220
+
+#define SDR0_AMP0 0x0240
+#define SDR0_AMP0_PRIORITY 0xFFFF0000
+#define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00
+#define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF
+
+#define SDR0_AMP1 0x0241
+#define SDR0_AMP1_PRIORITY 0xFC000000
+#define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000
+#define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF
+
+#define SDR0_MIRQ0 0x0260
+#define SDR0_MIRQ1 0x0261
+#define SDR0_MALTBL 0x0280
+#define SDR0_MALRBL 0x02A0
+#define SDR0_MALTBS 0x02C0
+#define SDR0_MALRBS 0x02E0
+
+/* Reserved for Customer Use */
+#define SDR0_CUST0 0x4000
+#define SDR0_CUST0_AUTONEG_MASK 0x8000000
+#define SDR0_CUST0_NO_AUTONEG 0x0000000
+#define SDR0_CUST0_AUTONEG 0x8000000
+#define SDR0_CUST0_ETH_FORCE_MASK 0x6000000
+#define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000
+#define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000
+#define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000
+#define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000
+#define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000
+#define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000
+
+#define SDR0_SDSTP4 0x4001
+#define SDR0_CUST1 0x4002
+#define SDR0_SDSTP5 0x4003
+#define SDR0_CUST2 0x4004
+#define SDR0_SDSTP6 0x4005
+#define SDR0_CUST3 0x4006
+#define SDR0_SDSTP7 0x4007
+
+#define SDR0_PFC0 0x4100
+#define SDR0_PFC0_GPIO_0 0x80000000
+#define SDR0_PFC0_PCIX0REQ2_N 0x00000000
+#define SDR0_PFC0_GPIO_1 0x40000000
+#define SDR0_PFC0_PCIX0REQ3_N 0x00000000
+#define SDR0_PFC0_GPIO_2 0x20000000
+#define SDR0_PFC0_PCIX0GNT2_N 0x00000000
+#define SDR0_PFC0_GPIO_3 0x10000000
+#define SDR0_PFC0_PCIX0GNT3_N 0x00000000
+#define SDR0_PFC0_GPIO_4 0x08000000
+#define SDR0_PFC0_PCIX1REQ2_N 0x00000000
+#define SDR0_PFC0_GPIO_5 0x04000000
+#define SDR0_PFC0_PCIX1REQ3_N 0x00000000
+#define SDR0_PFC0_GPIO_6 0x02000000
+#define SDR0_PFC0_PCIX1GNT2_N 0x00000000
+#define SDR0_PFC0_GPIO_7 0x01000000
+#define SDR0_PFC0_PCIX1GNT3_N 0x00000000
+#define SDR0_PFC0_GPIO_8 0x00800000
+#define SDR0_PFC0_PERREADY 0x00000000
+#define SDR0_PFC0_GPIO_9 0x00400000
+#define SDR0_PFC0_PERCS1_N 0x00000000
+#define SDR0_PFC0_GPIO_10 0x00200000
+#define SDR0_PFC0_PERCS2_N 0x00000000
+#define SDR0_PFC0_GPIO_11 0x00100000
+#define SDR0_PFC0_IRQ0 0x00000000
+#define SDR0_PFC0_GPIO_12 0x00080000
+#define SDR0_PFC0_IRQ1 0x00000000
+#define SDR0_PFC0_GPIO_13 0x00040000
+#define SDR0_PFC0_IRQ2 0x00000000
+#define SDR0_PFC0_GPIO_14 0x00020000
+#define SDR0_PFC0_IRQ3 0x00000000
+#define SDR0_PFC0_GPIO_15 0x00010000
+#define SDR0_PFC0_IRQ4 0x00000000
+#define SDR0_PFC0_GPIO_16 0x00008000
+#define SDR0_PFC0_IRQ5 0x00000000
+#define SDR0_PFC0_GPIO_17 0x00004000
+#define SDR0_PFC0_PERBE0_N 0x00000000
+#define SDR0_PFC0_GPIO_18 0x00002000
+#define SDR0_PFC0_PCI0GNT0_N 0x00000000
+#define SDR0_PFC0_GPIO_19 0x00001000
+#define SDR0_PFC0_PCI0GNT1_N 0x00000000
+#define SDR0_PFC0_GPIO_20 0x00000800
+#define SDR0_PFC0_PCI0REQ0_N 0x00000000
+#define SDR0_PFC0_GPIO_21 0x00000400
+#define SDR0_PFC0_PCI0REQ1_N 0x00000000
+#define SDR0_PFC0_GPIO_22 0x00000200
+#define SDR0_PFC0_PCI1GNT0_N 0x00000000
+#define SDR0_PFC0_GPIO_23 0x00000100
+#define SDR0_PFC0_PCI1GNT1_N 0x00000000
+#define SDR0_PFC0_GPIO_24 0x00000080
+#define SDR0_PFC0_PCI1REQ0_N 0x00000000
+#define SDR0_PFC0_GPIO_25 0x00000040
+#define SDR0_PFC0_PCI1REQ1_N 0x00000000
+#define SDR0_PFC0_GPIO_26 0x00000020
+#define SDR0_PFC0_PCI2GNT0_N 0x00000000
+#define SDR0_PFC0_GPIO_27 0x00000010
+#define SDR0_PFC0_PCI2GNT1_N 0x00000000
+#define SDR0_PFC0_GPIO_28 0x00000008
+#define SDR0_PFC0_PCI2REQ0_N 0x00000000
+#define SDR0_PFC0_GPIO_29 0x00000004
+#define SDR0_PFC0_PCI2REQ1_N 0x00000000
+#define SDR0_PFC0_GPIO_30 0x00000002
+#define SDR0_PFC0_UART1RX 0x00000000
+#define SDR0_PFC0_GPIO_31 0x00000001
+#define SDR0_PFC0_UART1TX 0x00000000
+
+#define SDR0_PFC1 0x4101
+#define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000
+#define SDR0_PFC1_UART1_DSR_DTR 0x00000000
+#define SDR0_PFC1_UART1_CTS_RTS 0x02000000
+#define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
+#define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
+#define SDR0_PFC1_UART2_IN_SERVICE 0x01000000
+#define SDR0_PFC1_ETH_GIGA_MASK 0x00200000
+#define SDR0_PFC1_ETH_10_100 0x00000000
+#define SDR0_PFC1_ETH_GIGA 0x00200000
+#define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21)
+#define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
+#define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
+#define SDR0_PFC1_CPU_NO_TRACE 0x00000000
+#define SDR0_PFC1_CPU_TRACE 0x00080000
+#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
+#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
+
+#define SDR0_MFR 0x4300
+#endif /* CONFIG_440SPE */
+
+
#define SDR0_SDCS_SDD (0x80000000 >> 31)
#if defined(CONFIG_440GP)
@@ -1159,7 +2430,7 @@
/*-----------------------------------------------------------------------------+
| Clocking
+-----------------------------------------------------------------------------*/
-#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP)
+#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
@@ -1498,6 +2769,9 @@ typedef struct {
unsigned long freqOPB;
unsigned long freqEPB;
unsigned long freqPCI;
+#ifdef CONFIG_440SPE
+ unsigned long freqDDR;
+#endif
unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
unsigned long pciClkSync; /* PCI clock is synchronous */
} PPC440_SYS_INFO;
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index d6d33b6..ec2e362 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -133,12 +133,21 @@ typedef struct emac_4xx_hw_st {
#define EMAC_NUM_DEV 4
#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
defined(CONFIG_NET_MULTI) && \
- !defined(CONFIG_440SP)
+ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
#define EMAC_NUM_DEV 2
#else
#define EMAC_NUM_DEV 1
#endif
+#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
+#define EMAC_STACR_OC_MASK (0x00008000)
+#else
+#define EMAC_STACR_OC_MASK (0x00000000)
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define SDR0_PFC1_EM_1000 (0x00200000)
+#endif
/*ZMII Bridge Register addresses */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
@@ -323,7 +332,7 @@ typedef struct emac_4xx_hw_st {
#define EMAC_M0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
@@ -424,8 +433,21 @@ typedef struct emac_4xx_hw_st {
/* STA CONTROL REG */
#define EMAC_STACR_OC (0x00008000)
#define EMAC_STACR_PHYE (0x00004000)
+
+#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
+#define EMAC_STACR_INDIRECT_MODE (0x00002000)
+#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
+#define EMAC_STACR_READ (0x00001000) /* $BUC */
+#define EMAC_STACR_OP_MASK (0x00001800)
+#define EMAC_STACR_MDIO_ADDR (0x00000000)
+#define EMAC_STACR_MDIO_WRITE (0x00000800)
+#define EMAC_STACR_MDIO_READ (0x00001800)
+#define EMAC_STACR_MDIO_READ_INC (0x00001000)
+#else
#define EMAC_STACR_WRITE (0x00002000)
#define EMAC_STACR_READ (0x00001000)
+#endif
+
#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
#define EMAC_STACR_CLK_66MHZ (0x00000400)
#define EMAC_STACR_CLK_100MHZ (0x00000C00)
diff --git a/include/usb.h b/include/usb.h
index 39d7f23..bf71554 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -108,6 +108,7 @@ struct usb_interface_descriptor {
unsigned char iInterface;
unsigned char no_of_ep;
+ unsigned char num_altsetting;
unsigned char act_altsetting;
struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
} __attribute__ ((packed));
diff --git a/include/xyzModem.h b/include/xyzModem.h
index 4ec10b5..f437bbd 100644
--- a/include/xyzModem.h
+++ b/include/xyzModem.h
@@ -97,7 +97,10 @@ typedef struct {
#endif
} connection_info_t;
+#ifndef BOOL_WAS_DEFINED
+#define BOOL_WAS_DEFINED
typedef unsigned int bool;
+#endif
#define false 0
#define true 1