diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-mx50/mx50.h | 30 | ||||
| -rw-r--r-- | include/configs/mx50_arm2.h | 30 | ||||
| -rw-r--r-- | include/configs/mx50_arm2_lpddr2.h | 30 | ||||
| -rw-r--r-- | include/lcd.h | 39 |
4 files changed, 129 insertions, 0 deletions
diff --git a/include/asm-arm/arch-mx50/mx50.h b/include/asm-arm/arch-mx50/mx50.h index d5e0d2c..2395252 100644 --- a/include/asm-arm/arch-mx50/mx50.h +++ b/include/asm-arm/arch-mx50/mx50.h @@ -43,6 +43,7 @@ #define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) #define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) #define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000) +#define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000) /* * SPBA global module enabled #0 @@ -135,6 +136,35 @@ #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) /* + * Some of i.MX50 SoC registers are associated with four addresses + * used for different operations - read/write, set, clear and toggle bits. + * + * Some of registers do not implement such feature and, thus, should be + * accessed/manipulated via single address in common way. + */ +#define REG_RD(base, reg) \ + (*(volatile unsigned int *)((base) + (reg))) +#define REG_WR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg))) = (value)) +#define REG_SET(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _SET))) = (value)) +#define REG_CLR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _CLR))) = (value)) +#define REG_TOG(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _TOG))) = (value)) + +#define REG_RD_ADDR(addr) \ + (*(volatile unsigned int *)((addr))) +#define REG_WR_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr))) = (value)) +#define REG_SET_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0x4)) = (value)) +#define REG_CLR_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0x8)) = (value)) +#define REG_TOG_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0xc)) = (value)) + +/* * Memory regions and CS */ #define CSD0_BASE_ADDR 0x70000000 diff --git a/include/configs/mx50_arm2.h b/include/configs/mx50_arm2.h index 4c23b95..c7f8faf 100644 --- a/include/configs/mx50_arm2.h +++ b/include/configs/mx50_arm2.h @@ -163,6 +163,36 @@ #define CONFIG_DISCOVER_PHY /* +#define CONFIG_SPLASH_SCREEN +*/ + +/* + * SPLASH SCREEN Configs + */ +#ifdef CONFIG_SPLASH_SCREEN + #define CONFIG_LCD + #undef LCD_TEST_PATTERN + #define CONFIG_FB_BASE (TEXT_BASE + 0x300000) + #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + /* #define CONFIG_SPLASH_IS_IN_MMC 1 */ + #define LCD_BPP LCD_MONOCHROME + /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + + #define CONFIG_MXC_EPDC 1 + + #define CONFIG_WORKING_BUF_ADDR (TEXT_BASE + 0x100000) + #define CONFIG_WAVEFORM_BUF_ADDR (TEXT_BASE + 0x200000) + #define CONFIG_WAVEFORM_FILE_OFFSET 0x100000 + #define CONFIG_WAVEFORM_FILE_SIZE 0xB4000 + #define CONFIG_WAVEFORM_FILE_IN_MMC +#endif + +#ifdef CONFIG_SPLASH_IS_IN_MMC + #define CONFIG_SPLASH_IMG_OFFSET 0x4c000 + #define CONFIG_SPLASH_IMG_SIZE 0x19000 +#endif + +/* * I2C Configs */ #define CONFIG_CMD_I2C 1 diff --git a/include/configs/mx50_arm2_lpddr2.h b/include/configs/mx50_arm2_lpddr2.h index a5683ad..6efe6a6 100644 --- a/include/configs/mx50_arm2_lpddr2.h +++ b/include/configs/mx50_arm2_lpddr2.h @@ -164,6 +164,36 @@ #define CONFIG_DISCOVER_PHY /* +#define CONFIG_SPLASH_SCREEN +*/ + +/* + * SPLASH SCREEN Configs + */ +#ifdef CONFIG_SPLASH_SCREEN + #define CONFIG_LCD + #undef LCD_TEST_PATTERN + #define CONFIG_FB_BASE (TEXT_BASE + 0x300000) + #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + /* #define CONFIG_SPLASH_IS_IN_MMC 1 */ + #define LCD_BPP LCD_MONOCHROME + /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + + #define CONFIG_MXC_EPDC 1 + + #define CONFIG_WORKING_BUF_ADDR (TEXT_BASE + 0x100000) + #define CONFIG_WAVEFORM_BUF_ADDR (TEXT_BASE + 0x200000) + #define CONFIG_WAVEFORM_FILE_OFFSET 0x100000 + #define CONFIG_WAVEFORM_FILE_SIZE 0xB4000 + #define CONFIG_WAVEFORM_FILE_IN_MMC +#endif + +#ifdef CONFIG_SPLASH_IS_IN_MMC + #define CONFIG_SPLASH_IMG_OFFSET 0x4c000 + #define CONFIG_SPLASH_IMG_SIZE 0x19000 +#endif + +/* * I2C Configs */ #define CONFIG_CMD_I2C 1 diff --git a/include/lcd.h b/include/lcd.h index afb99ba..062e024 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -203,6 +203,45 @@ typedef struct vidinfo { ushort *cmap; } vidinfo_t; +#elif defined(CONFIG_MXC_EPDC) + +struct waveform_modes { + int mode_init; + int mode_du; + int mode_gc4; + int mode_gc8; + int mode_gc16; + int mode_gc32; +}; + +struct epdc_data_struct { + /* EPDC buffer pointers */ + u_long working_buf_addr; + u_long waveform_buf_addr; + + /* Waveform mode definitions */ + struct waveform_modes wv_modes; +}; + +typedef struct vidinfo { + u_long vl_refresh; /* Refresh Rate Hz */ + u_long vl_row; /* resolution in x */ + u_long vl_col; /* resolution in y */ + u_long vl_pixclock; /* pixel clock in picoseconds */ + u_long vl_left_margin; /* Horizontal back porch */ + u_long vl_right_margin; /* Horizontal front porch */ + u_long vl_upper_margin; /* Vertical back porch */ + u_long vl_lower_margin; /* Vertical front porch */ + u_long vl_hsync; /* Horizontal sync pulse length */ + u_long vl_vsync; /* Vertical sync pulse length */ + u_long vl_sync; /* Polarity on data enable */ + u_long vl_mode; /* Video Mode */ + u_long vl_flag; + u_char vl_bpix; + ushort *cmap; + struct epdc_data_struct epdc_data; +} vidinfo_t; + #else typedef struct vidinfo { |