diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/MPC8569MDS.h | 64 | ||||
| -rw-r--r-- | include/fsl_nfc.h | 86 |
2 files changed, 135 insertions, 15 deletions
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index ae2fc19..6cf807b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -62,6 +62,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_NAND 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 +#endif + /* * Only possible on E500 Version 2 or newer cores. */ @@ -74,16 +80,29 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_END 0x00400000 /* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif + #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) @@ -152,8 +171,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE /*Chip select 0 - Flash*/ -#define CONFIG_SYS_BR0_PRELIM 0xfe000801 -#define CONFIG_SYS_OR0_PRELIM 0xfe000ff7 +#define CONFIG_FLASH_BR_PRELIM 0xfe000801 +#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 /*Chip select 1 - BCSR*/ #define CONFIG_SYS_BR1_PRELIM 0xf8000801 @@ -175,12 +194,33 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO /* Chip select 3 - NAND */ +#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xFC000000 +#else +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#endif + +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START \ + (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -200,8 +240,18 @@ extern unsigned long get_clock_freq(void); | OR_FCM_SCY_1 \ | OR_FCM_TRLX \ | OR_FCM_EHTR) + +#ifdef CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#endif /* * SDRAM on the LocalBus @@ -437,10 +487,18 @@ extern unsigned long get_clock_freq(void); /* * Environment */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif +#else #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h index da5be37..279aaa5 100644 --- a/include/fsl_nfc.h +++ b/include/fsl_nfc.h @@ -1,5 +1,4 @@ /* - * * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com> * * See file CREDITS for list of people who contributed to this @@ -25,21 +24,57 @@ #define __FSL_NFC_H /* + * TODO: Use same register defs for nand_spl mxc nand driver + * and mtd mxc nand driver. + * * Register map and bit definitions for the Freescale NAND Flash - * Controller present in i.MX31 and other devices. + * Controller present in various i.MX devices. + * + * MX31 and MX27 have version 1 which has + * 4 512 byte main buffers and + * 4 16 byte spare buffers + * to support up to 2K byte pagesize nand. + * Reading or writing a 2K page requires 4 FDI/FDO cycles. + * + * MX25 has version 1.1 which has + * 8 512 byte main buffers and + * 8 64 byte spare buffers + * to support up to 4K byte pagesize nand. + * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. + * Also some of registers are moved and/or changed meaning as seen below. */ +#if defined(CONFIG_MX31) || defined(CONFIG_MX27) +#define MXC_NFC_V1 +#elif defined(CONFIG_MX25) +#define MXC_NFC_V1_1 +#else +#warning "MXC NFC version not defined" +#endif + +#if defined(MXC_NFC_V1) +#define NAND_MXC_NR_BUFS 4 +#define NAND_MXC_SPARE_BUF_SIZE 16 +#define NAND_MXC_REG_OFFSET 0xe00 +#define NAND_MXC_2K_MULTI_CYCLE 1 +#elif defined(MXC_NFC_V1_1) +#define NAND_MXC_NR_BUFS 8 +#define NAND_MXC_SPARE_BUF_SIZE 64 +#define NAND_MXC_REG_OFFSET 0x1e00 +#else +#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver" +#endif struct fsl_nfc_regs { - u32 main_area0[128]; /* @0x000 */ - u32 main_area1[128]; - u32 main_area2[128]; - u32 main_area3[128]; - u32 spare_area0[4]; - u32 spare_area1[4]; - u32 spare_area2[4]; - u32 spare_area3[4]; - u32 reserved1[64 - 16 + 64 * 5]; - u16 bufsiz; /* @ 0xe00 */ + u32 main_area[NAND_MXC_NR_BUFS][512/4]; + u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4]; + /* + * reserved size is offset of nfc registers + * minus total main and spare sizes + */ + u8 reserved1[NAND_MXC_REG_OFFSET + - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; +#if defined(MXC_NFC_V1) + u16 bufsiz; u16 reserved2; u16 buffer_address; u16 flash_add; @@ -54,6 +89,30 @@ struct fsl_nfc_regs { u16 nand_flash_wr_pr_st; u16 nand_flash_config1; u16 nand_flash_config2; +#elif defined(MXC_NFC_V1_1) + u16 reserved2[2]; + u16 buffer_address; + u16 flash_add; + u16 flash_cmd; + u16 configuration; + u16 ecc_status_result; + u16 ecc_status_result2; + u16 spare_area_size; + u16 nf_wr_prot; + u16 reserved3[2]; + u16 nand_flash_wr_pr_st; + u16 nand_flash_config1; + u16 nand_flash_config2; + u16 reserved4; + u16 unlock_start_blk_add0; + u16 unlock_end_blk_add0; + u16 unlock_start_blk_add1; + u16 unlock_end_blk_add1; + u16 unlock_start_blk_add2; + u16 unlock_end_blk_add2; + u16 unlock_start_blk_add3; + u16 unlock_end_blk_add3; +#endif }; /* @@ -98,6 +157,9 @@ struct fsl_nfc_regs { */ #define NFC_INT 0x8000 +#ifdef MXC_NFC_V1_1 +#define NFC_4_8N_ECC (1 << 0) +#endif #define NFC_SP_EN (1 << 2) #define NFC_ECC_EN (1 << 3) #define NFC_INT_MSK (1 << 4) |